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HEF4069UBP-HEF4069UBT-HEF4069UBTT
Hex inverter
1. General descriptionThe HEF4069UB is a general purpose hex inverter. Each inverter has a single stage.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits Fully static operation5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C and 40 C to +125C Complies with JEDEC standard JESD 13-B
3. Applications Oscillator
4. Ordering information
HEF4069UB
Hex inverter
Rev. 8 — 16 November 2011 Product data sheet
Table 1. Ordering informationAll types operate from 40 C to +125 C.
HEF4069UBP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
HEF4069UBT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
HEF4069UBTT TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
NXP Semiconductors HEF4069UB
Hex inverter
5. Functional diagram
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin description1A to 6A 1, 3, 5, 9, 11, 13 input
1Y to 6Y 2, 4, 6, 8, 10, 12 output
VSS 7 ground (0 V)
VDD 14 supply voltage
NXP Semiconductors HEF4069UB
Hex inverter
7. Limiting values[1] For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K.
[2] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.
[3] For TSSOP14 packages: above Tamb = 60 C, Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 3. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +18 V
IIK input clamping current VI< 0.5 V or VI >VDD + 0.5 V - 10 mA input voltage 0.5 VDD + 0.5 V
IOK output clamping current VO< 0.5 V or VO >VDD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +125 C
Ptot total power dissipation Tamb = 40 C to +125 C
DIP14 [1] -750 mW
SO14 [2] -500 mW
TSSOP14 [3] -500 mW power dissipation per output - 100 mW
Table 4. Recommended operating conditionsVDD supply voltage 3 - 15 V input voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +125 C
NXP Semiconductors HEF4069UB
Hex inverter
9. Static characteristicsTable 5. Static characteristicsVSS = 0 V; VI =VSS or VDD; unless otherwise specified.
VIH HIGH-level
input voltage IO <1A 5V 4 - 4 -4 -4 - VV 8 - 8 -8 -8 - VV 12.5 - 12.5 - 12.5 - 12.5 - V
VIL LOW-level
input voltage IO <1A 5V - 1-1-1-1 VV - 2-2-2-2 VV - 2.5 - 2.5 - 2.5 - 2.5 V
VOH HIGH-level
output voltage IO <1A 5V 4.95 - 4.95 - 4.95 - 4.95 - VV 9.95 - 9.95 - 9.95 - 9.95 - VV 14.95 - 14.95 - 14.95 - 14.95 - V
VOL LOW-level
output voltage IO <1A 5V - 0.05 - 0.05 - 0.05 - 0.05 VV - 0.05 - 0.05 - 0.05 - 0.05 VV - 0.05 - 0.05 - 0.05 - 0.05 V
IOH HIGH-level
output current
VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA
VO = 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA
VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA
VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA
IOL LOW-level
output current
VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA
VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA input leakage
currentV - 0.1 - 0.1 - 1.0 - 1.0 A
IDD supply current all valid input
combinations; =0AV - 0.25 - 0.25 - 7.5 - 7.5 AV - 0.5 - 0.5 - 15.0 - 15.0 AV - 1.0 - 1.0 - 30.0 - 30.0 A input
capacitance
digital inputs - - - 7.5 - - - - pF
NXP Semiconductors HEF4069UB
Hex inverter
10. Dynamic characteristics[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
Table 6. Dynamic characteristicsTamb = 25 C; for waveforms see Figure 4; for test circuit see Figure5.
tPHL HIGH to LOW
propagation delay
nA to nY; 5V 18 ns + (0.55 ns/pF)CL -45 90 nsV 9 ns + (0.23 ns/pF)CL -20 40 nsV 7 ns + (0.16 ns/pF)CL -15 25 ns
tPLH LOW to HIGH
propagation delay
nA to nY 5V 13 ns + (0.55 ns/pF)CL -40 80 nsV 9 ns + (0.23 ns/pF)CL -20 40 nsV 7 ns + (0.16 ns/pF)CL -15 30 ns
tTHL HIGH to LOW output
transition time
output nY 5V 10 ns + (1.00 ns/pF)CL - 60 120 nsV 9 ns + (0.42 ns/pF)CL -30 60 nsV 6 ns + (0.28 ns/pF)CL -20 40 ns
tTLH LOW to HIGH output
transition time
output nY 5V 10 ns + (1.00 ns/pF)CL - 60 120 nsV 9 ns + (0.42 ns/pF)CL -30 60 nsV 6 ns + (0.28 ns/pF)CL -20 40 ns
Table 7. Dynamic power dissipationVSS = 0 V; tr = tf 20 ns; Tamb = 25 C. dynamic power dissipation 5V PD = 600 fi + (fo CL) VDD2 (W) fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
(fo CL) = sum of the outputs;
VDD = supply voltage in V.V PD = 4000 fi + (fo CL) VDD2 (W)V PD = 22000 fi + (fo CL) VDD2 (W)
NXP Semiconductors HEF4069UB
Hex inverter
11. Waveforms
Table 8. Test data V to 15V VSS or VDD 20ns 50 pF
NXP Semiconductors HEF4069UB
Hex inverter
11.1 Transfer characteristicsNXP Semiconductors HEF4069UB
Hex inverter
12. Application informationSome examples of applications for the HEF4069UB.
Figure 7 shows an astable relaxation oscillator using two HEF4069UB inverters and 2
BAW62 diodes. The oscillation frequency is mainly determined by R1 C1, provided << R2 and R2 C2 << R1 C1.
The function of R2 is to minimize the influence of the forward voltage across the protection
diodes on the frequency; C2 is a stray (parasitic) capacitance.
The period Tp is given by Tp =T1 +T2,
where:
VST = the signal threshold level of the inverter.
The period is fairly independent of VDD, VST and temperature. The duty factor, however, is
influenced by VST.
