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HEF4044BT ,Quadruple R/S latch with 3-state outputsLogic diagram (one latch).Fig.3
HEF4044BT ,Quadruple R/S latch with 3-state outputsGeneral descriptionThe HEF4044B is a quad R/S latch with 3-state outputs, with a common output enab ..
HEF4044BT ,Quadruple R/S latch with 3-state outputsINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC04 LOCMOS HE40 ..
HEF4046BD ,Phase-locked loopfunctional description see further on in thisdata.Fig.1 Functional diagram.FAMILY DATAHEF4046BP(N) ..
HEF4046BP ,Phase-locked loopPin configurationHEF4046B All information provided in this document is subject to legal disclaimers ..
HEF4046BT ,Phase-locked loopINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC04 LOCMOS HE40 ..
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HEF4044BT
Quad R/S latch with 3-state outputs
1. General description
The HEF4044B is a quad R/S latch with 3-state outputs, with a common output enable
input (OE). Each latch has an active LOW set input (1S to 4S), an active LOW reset input
(1R to 4R) and an active HIGH 3-state output (1Q to 4Q).
When OE is HIGH, the latch output (nQ) is determined by the nR and nS inputs as shown
in Table 3. When OE is LOW, the latch outputs are in the high impedance OFF-state. OE
does not affect the state of the latch. The high impedance off-state feature allows common
bussing of the outputs.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B
3. Applications Four-bit storage with output enable
4. Ordering information
HEF4044B
Quad R/S latch with 3-state outputs
Rev. 10 — 18 November 2011 Product data sheet
Table 1. Ordering information
All types operate from 40 C to +85 C.
HEF4044BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4044BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
NXP Semiconductors HEF4044B
Quad R/S latch with 3-state outputs
5. Functional diagram
6. Pinning information
6.1 Pinning
NXP Semiconductors HEF4044B
Quad R/S latch with 3-state outputs
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state.
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
Table 2. Pin description
n.c. 2 not connected
1S to 4S 3, 7, 11, 15 set input (active LOW)
1R to 4R 4, 6, 12, 14 reset input (active LOW) 5 common output enable input
VSS 8 ground supply voltage
1Q to 4Q 13, 9, 10, 1 3-state buffered latch output
VDD 16 supply voltage
Table 3. Function table[1] X Z HH L L Hlatched
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +18 V
IIK input clamping current VI< 0.5 V or VI >VDD + 0.5 V - 10 mA input voltage 0.5 VDD + 0.5 V
IOK output clamping current VO< 0.5 V or VO >VDD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +85 C
Ptot total power dissipation Tamb 40 C to +85 C
DIP16 package [1]- 750 mW
SO16 package [2]- 500 mW
per output - 100 mW
NXP Semiconductors HEF4044B
Quad R/S latch with 3-state outputs
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating conditions
VDD supply voltage 3 - 15 V input voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V
VDD = 10 V - - 0.5 s/V
VDD = 15 V - - 0.08 s/V
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
VOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA input leakage current 15 V - 0.3 - 0.3 - 1.0 A
IOZ OFF-state output current nQ output HIGH;
returned to VDD
15 V - 1.6 - 1.6 - 12.0 A
nQ output LOW;
returned to VSS
15 V - 1.6 - 1.6 - 12.0 A
NXP Semiconductors HEF4044B
Quad R/S latch with 3-state outputs
11. Dynamic characteristics
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
IDD supply current IO = 0A 5 V - 20 - 20 - 150 A
10 V - 40 - 40 - 300 A
15 V - 80 - 80 - 600 A input capacitance - - - 7.5 - - pF
Table 6. Static characteristics …continued
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified.
tPHL HIGH to LOW
propagation delayto nQ; see
Figure4
5 V [1] 63 ns + (0.55 ns/pF)CL - 90 185 ns
10 V 29 ns + (0.23 ns/pF)CL - 4080ns
15 V 22 ns + (0.16 ns/pF)CL - 3060ns
tPLH LOW to HIGH
propagation delayto nQ;
see Figure4
5 V [1] 63 ns + (0.55 ns/pF)CL - 90 180 ns
10 V 29 ns + (0.23 ns/pF)CL - 4080ns
15 V 22 ns + (0.16 ns/pF)CL - 3060ns transition time see Figure4 5 V [1] 10 ns + (1.00 ns/pF)CL - 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL - 3060ns
15 V 6 ns + (0.28 ns/pF)CL - 2040ns
tPHZ HIGH to OFF-state
propagation delay
OE nQ;
see Figure5
5 V - 50 100 ns
10 V - 30 60 ns
15 V - 25 50 ns
tPLZ LOW to OFF-state
propagation delay
OE nQ;
see Figure5
5 V - 30 60 ns
10 V - 25 45 ns
15 V - 20 40 ns
tPZH OFF-state to HIGH
propagation delay
OE nQ;
see Figure5
5 V - 50 100 ns
10 V - 25 50 ns
15 V - 20 40 ns
tPZL OFF-state to LOW
propagation delay
OE nQ;
see Figure5
5 V - 50 95 ns
10 V - 25 45 ns
15 V - 20 35 ns pulse width nS input LOW;
minimum width;
see Figure4
5 V 3015- ns
10 V 2010- ns
15 V 16 8 - ns
nR input LOW;
minimum width;
see Figure4
5 V 3015- ns
10 V 2010- ns
15 V 16 8 - ns
NXP Semiconductors HEF4044B
Quad R/S latch with 3-state outputs
12. Waveforms
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. dynamic power
dissipation
5 V PD = 1300  fi + (fo  CL)  VDD2 fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo  CL) = sum of the outputs.
10 V PD = 5200  fi + (fo  CL)  VDD2
15 V PD = 12900  fi + (fo  CL)  VDD2
NXP Semiconductors HEF4044B
Quad R/S latch with 3-state outputs
Table 9. Measurement points
5 V to 15 V VDD or VSS 0.5VDD 0.5VDD 0.1VDD 0.9VDD

Partno	Mfg	Dc	Qty	Available	Descript
HEF4044BT		N/a	499	avai	Quadruple R/S latch with 3-state outputs