HEF4040BT ,12-stage binary ripple counterLogic diagram 1 2 4 8 16 32 64 128 256 512 1024 2048 4096CP inputMR inputQ0Q1Q2Q3Q4Q5Q6Q7Q8Q9Q10Q11 ..
HEF4041BD ,Quadruple true/complement buffer
HEF4041BD ,Quadruple true/complement buffer
HEF4041BDB ,Quadruple true/complement buffer
HEF4041BDB ,Quadruple true/complement buffer
HEF4041BDB ,Quadruple true/complement buffer
HM6208HJP-35 , 65,536-word ´ 4-bit High Speed CMOS Static RAM
HM6208HLJP-25 , 65,536-word ´ 4-bit High Speed CMOS Static RAM
HM6208HP-45 , 65,536-word ´ 4-bit High Speed CMOS Static RAM
HM621400HJP-12 , 4M High Speed SRAM (4-Mword x 1-bit)
HM6216255HCTT-10 , 4M High Speed SRAM (256-kword x 16-bit)
HM6216255HJP-10 , 4M high Speed SRAM (256-kword x 16-bit)
HEF4040-HEF4040BD-HEF4040BP-HEF4040BT
12-stage binary ripple counter
1. General descriptionThe HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The
counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter
stages and forces all outputs LOW, independent of CP. Each counter stage is a static
toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its
Schmitt trigger action.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits Tolerant of slow clock rise and fall time Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B
3. Applications Frequency dividing circuits Time delay circuits Control counters
4. Ordering information
HEF4040B
12-stage binary ripple counter
Rev. 8 — 17 November 2011 Product data sheet
Table 1. Ordering informationAll types operate from 40 C to +85 C.
HEF4040BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4040BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
NXP Semiconductors HEF4040B
12-stage binary ripple counter
5. Functional diagramNXP Semiconductors HEF4040B
12-stage binary ripple counter
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin descriptionVSS 8 ground supply voltage
Q0 to Q11 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 parallel output 10 clock input (HIGH-to-LOW edge-triggered) 11 master reset input (active HIGH)
VDD 16 supply voltage
NXP Semiconductors HEF4040B
12-stage binary ripple counter
7. Limiting values[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions
9. Static characteristics
Table 3. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +18 V
IIK input clamping current VI< 0.5 V or VI >VDD + 0.5 V - 10 mA input voltage 0.5 VDD + 0.5 V
IOK output clamping current VO< 0.5 V or VO >VDD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +85 C
Ptot total power dissipation DIP16 package [1]- 750 mW
SO16 package [2]- 500 mW power dissipation per output - 100 mW
Table 4. Recommended operating conditionsVDD supply voltage 3 - 15 V input voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate VDD = 5V --3.75 ms/V
VDD = 10 V --0.5 ms/V
VDD = 15 V --0.08 ms/V
Table 5. Static characteristicsVSS = 0 V; VI = VSS or VDD; unless otherwise specified.
VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
NXP Semiconductors HEF4040B
12-stage binary ripple counter
10. Dynamic characteristicsVOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
ILI input leakage current 15 V - 0.3 - 0.3 - 1.0 A
IDD supply current IO = 0A 5 V - 20 - 20 - 150 A
10 V - 40 - 40 - 300 A
15 V - 80 - 80 - 600 A input capacitance - - - - 7.5 - - pF
Table 5. Static characteristics …continuedVSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Table 6. Dynamic characteristicsVSS = 0 V; Tamb = 25 C; unless otherwise specified; for test circuit see Figure6.
tPHL HIGH to LOW
propagation delay Q0
see Figure5
5 V 78 ns + (0.55 ns/pF)CL - 105 210 ns
10 V 34 ns + (0.23 ns/pF)CL -45 90 ns
15 V 27 ns + (0.16 ns/pF)CL -35 70 ns
Qn Qn + 1 5 V [2] (0.55 ns/pF)CL -35 70 ns
10 V [2] (0.23 ns/pF)CL -15 30 ns
15 V [2] (0.16 ns/pF)CL -10 20 ns
MR Qn
see Figure5
5 V 63 ns + (0.55 ns/pF)CL - 90 180 ns
10 V 29 ns + (0.23 ns/pF)CL -40 80 ns
15 V 22 ns + (0.16 ns/pF)CL -30 60 ns
tPLH LOW to HIGH
propagation delay Q0
see Figure5
5 V 58 ns + (0.55 ns/pF)CL - 85 170 ns
10 V 29 ns + (0.23 ns/pF)CL -40 80 ns
15 V 22 ns + (0.16 ns/pF)CL -30 60 ns
Qn Qn + 1 5 V [2] (0.55 ns/pF)CL -35 70 ns
10 V [2] (0.23 ns/pF)CL -15 30 ns
15 V [2] (0.16 ns/pF)CL -10 20 ns
NXP Semiconductors HEF4040B
12-stage binary ripple counter[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] For loads other than 50 pF at the nth output, use the slope given.
[3] tt is the same as tTHL and tTLH. transition time see Figure5 5 V [3] 10 ns + (1.00 ns/pF)CL - 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL -30 60 ns
15 V 6 ns + (0.28 ns/pF)CL -20 40 ns pulse width CP input HIGH;
minimum width;
see Figure5
5 V 5025- ns
10 V 3015- ns
15 V 2010- ns
MR input HIGH;
minimum width;
see Figure5
5 V 4020- ns
10 V 3015- ns
15 V 2010- ns
trec recovery time MR input;
see Figure5
5 V 4020- ns
10 V 3015- ns
15 V 2010- ns
fmax maximum
frequency
CP input;
see Figure5
5 V 1020- MHz
10 V 1530- MHz
15 V 2550- MHz
Table 6. Dynamic characteristics …continuedVSS = 0 V; Tamb = 25 C; unless otherwise specified; for test circuit see Figure6.
Table 7. Dynamic power dissipation PDPD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. dynamic power
dissipation
5 V PD = 400 fi + (fo CL) VDD2 fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo CL) = sum of the outputs.
10 V PD = 2000 fi + (fo CL) VDD2
15 V PD = 5200 fi + (fo CL) VDD2
NXP Semiconductors HEF4040B
12-stage binary ripple counter
11. Waveforms
Table 8. Measurement points5 V to 15 V VDD or VSS 0.5VDD 0.5VDD
