HEF4027BT Fast Delivery |IC PHOENIX CO.,LIMITED

HEF4027BT ,Dual JK flip-flopfeatures independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data ..
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HEF4027BT
Dual JK flip-flop
1. General description
The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct
(SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is
LOW, and transferred to the output on the positive-going edge of the clock. The active
HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and
override the J, K, and CP inputs. The outputs are buffered for best system performance.
Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B
3. Applications Registers Counters Control circuits
4. Ordering information
HEF4027B
Dual JK flip-flop
Rev. 9 — 18 November 2011 Product data sheet
Table 1. Ordering information
Tamb from 40 C to +85 C.
HEF4027BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4027BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
NXP Semiconductors HEF4027B
Dual JK flip-flop
5. Functional diagram
NXP Semiconductors HEF4027B
Dual JK flip-flop
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
Table 2. Pin description
VSS 8 ground supply voltage
1SD, 2SD 9, 7 asynchronous set-direct input (active HIGH)
1J, 2J 10, 6 synchronous input
1K, 2K 11, 5 synchronous input
1CD, 2CD 12, 4 asynchronous clear-direct input (active HIGH)
1CP, 2CP 13, 3 clock input (LOW-to-HIGH edge-triggered)
1Q, 2Q 14, 2 complement output
1Q, 2Q 15, 1 true output
VDD 16 supply voltage
Table 3. Function table[1] X X X HL X LH X HH
NXP Semiconductors HEF4027B
Dual JK flip-flop
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.;  = positive-going transition.
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions  L L no change no change  HL HL  LH LH  HH nQ nQ
Table 3. Function table[1]
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +18 V
IIK input clamping current VI< 0.5 V or VI >VDD + 0.5 V - 10 mA input voltage 0.5 VDD + 0.5 V
IOK output clamping current VO< 0.5 V or VO >VDD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature in free air 40 +85 C
Ptot total power dissipation Tamb 40 C to +85 C
DIP16 package [1]- 750 mW
SO16 package [2]- 500 mW power dissipation per output - 100 mW
Table 5. Recommended operating conditions
VDD supply voltage 3 15 V input voltage 0 VDD V
Tamb ambient temperature in free air 40 +85 C
t/V input transition rise and fall rate VDD = 5 V - 3.75 s/V
VDD = 10 V - 0.5 s/V
VDD = 15 V - 0.08 s/V
NXP Semiconductors HEF4027B
Dual JK flip-flop
10. Static characteristicsTable 6. Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage IO < 1 A5 V- 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
VOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA input leakage current 15 V - 0.3 - 0.3 - 1.0 A
IDD supply current IO = 0A 5 V - 4.0 - 4.0 - 30 A
10 V - 8.0 - 8.0 - 60 A
15 V - 16.0 - 16.0 - 120 A input capacitance - - - - 7.5 - - pF
NXP Semiconductors HEF4027B
Dual JK flip-flop
11. Dynamic characteristicsTable 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.
tPHL HIGH to LOW
propagation delay
CP  Q, Q;
see Figure4
5 V 78 ns + (0.55 ns/pF)CL - 105 210 ns
10 V 29 ns + (0.23 ns/pF)CL - 4080ns
15 V 22 ns + (0.16 ns/pF)CL - 3060ns
CD  Q;
see Figure4
5 V 93 ns + (0.55 ns/pF)CL - 120 240 ns
10 V 33 ns + (0.23 ns/pF)CL - 4590ns
15 V 27 ns + (0.16 ns/pF)CL - 3570ns
SD  Q;
see Figure4
5 V 113 ns + (0.55 ns/pF)CL - 140 280 ns
10 V 44 ns + (0.23 ns/pF)CL -55 110 ns
15 V 32 ns + (0.16 ns/pF)CL - 4080ns
tPLH LOW to HIGH
propagation delay
CP  Q, Q;
see Figure4
5 V 58 ns + (0.55 ns/pF)CL - 85 170 ns
10 V 27 ns + (0.23 ns/pF)CL - 3570ns
15 V 22 ns + (0.16 ns/pF)CL - 3060ns
CD  Q;
see Figure4
5 V 48 ns + (0.55 ns/pF)CL - 75 150 ns
10 V 24 ns + (0.23 ns/pF)CL - 3570ns
15 V 17 ns + (0.16 ns/pF)CL - 2550ns
SD  Q;
see Figure4
5 V 43 ns + (0.55 ns/pF)CL - 70 140 ns
10 V 19 ns + (0.23 ns/pF)CL - 3060ns
15 V 17 ns + (0.16 ns/pF)CL - 2550ns transition time see Figure4 5 V [2] 10 ns + (1.00 ns/pF)CL - 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL - 3060ns
15 V 6 ns + (0.28 ns/pF)CL - 2040ns
tsu set-up time J, K  CP;
see Figure5
5 V 5025- ns
10 V 3010- ns
15 V 20 5 - ns hold time J, K  CP;
see Figure5
5 V 25 0 - ns
10 V 20 0 - ns
15 V 15 5 - ns pulse width CP LOW;
minimum width
see Figure5
5 V 8040- ns
10 V 3015- ns
15 V 2412- ns
SD, CD HIGH;
minimum width
see Figure6
5 V 9045- ns
10 V 4020- ns
15 V 3015- ns
trec recovery time SD, CD inputs;
see Figure6
5 V +20 15 - ns
10 V +15 10 - ns
15 V +10 5- ns
NXP Semiconductors HEF4027B
Dual JK flip-flop
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] tt is the same as tTLH and tTHL.
12. Waveforms
fmax maximum
frequency
CP input; =K = HIGH;
see Figure5
5 V 4 8 - MHz
10 V 12 25 - MHz
15 V 15 30 - MHz
Table 7. Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. dynamic power
dissipation
5 V PD = 900  fi + (fo  CL)  VDD2 fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
(fo  CL) = sum of the outputs.
10 V PD = 4500  fi + (fo  CL)  VDD2
15 V PD = 13200  fi + (fo  CL)  VDD2

Partno	Mfg	Dc	Qty	Available	Descript
HEF4027BT	NXP	N/a	30000	avai	Dual JK flip-flop