HCPL0661 ,High Speed-10 MBit/s Logic Gate OptocouplersFeatures Pulse transformer replacement Compact SO8 package Computer-peripheral interface Very high ..
HCPL-0661 ,HCMOS Compatible, High CMR, 10 MBd OptocouplersHHigh CMR, High Speed TTLCompatible Optocouplers6N137HCNW137 HCPL-0631HCNW2601 HCPL-0661Technical D ..
HCPL-0661 ,HCMOS Compatible, High CMR, 10 MBd OptocouplersHHigh CMR, High Speed TTLCompatible Optocouplers6N137HCNW137 HCPL-0631HCNW2601 HCPL-0661Technical D ..
HCPL-0661 ,HCMOS Compatible, High CMR, 10 MBd OptocouplersHHigh CMR, High Speed TTLCompatible Optocouplers6N137HCNW137 HCPL-0631HCNW2601 HCPL-0661Technical D ..
HCPL-0661 ,HCMOS Compatible, High CMR, 10 MBd OptocouplersHHigh CMR, High Speed TTLCompatible Optocouplers6N137HCNW137 HCPL-0631HCNW2601 HCPL-0661Technical D ..
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HD74121 , TTL HD74/HD74S Series
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HCPL0661
High Speed-10 MBit/s Logic Gate Optocouplers
HCPL0600, HCPL0601, HCPL0611, HCPL0630, HCPL0631, HCPL0661 High Speed-10 MBit/s Logic Gate Optocouplers July 2005 HCPL0600, HCPL0601, HCPL0611, HCPL0630, HCPL0631, HCPL0661 High Speed-10 MBit/s Logic Gate Optocouplers Single Channel: HCPL0600, HCPL0601, HCPL0611 Dual Channel: HCPL0630, HCPL0631, HCPL0661 ■ Switching power supplies Features ■ Pulse transformer replacement ■ Compact SO8 package ■ Computer-peripheral interface ■ Very high speed-10 MBit/s ■ Superior CMR Description ■ Fan-out of 8 over -40°C to +85°C The HCPL06XX optocouplers consist of an AlGaAS LED, opti- ■ Logic gate output cally coupled to a very high speed integrated photo-detector ■ Strobable output (single channel devices) logic gate with a strobable output (single channel devices). The ■ Wired OR-open collector devices are housed in a compact small-outline package. This output features an open collector, thereby permitting wired OR ■ U.L. recognized (File # E90700) outputs. The HCPL0600 and HCPL0601 output consists of ■ VDE approval pending bipolar transistors on a bipolar process while the HCPL0611, HCPL0630 and HCPL0631 output consists of bipolar transistors Applications on a CMOS process for reduced power consumption. The cou- ■ Ground loop elimination pled parameters are guaranteed over the temperature range of - 40°C to +85°C. A maximum input signal of 5 mA will provide a ■ LSTTL to TTL, LSTTL or 5-volt CMOS minimum output sink current of 13 mA (fan out of 8). An internal ■ Line receiver, data transmission noise shield provides superior common mode rejection. ■ Data multiplexing Package Dimensions 0.164 (4.16) 0.144 (3.66) Pin 1 0.202 (5.13) 0.182 (4.63) 0.019 (0.48) 0.010 (0.25) 0.143 (3.63) 0.006 (0.16) 0.123 (3.13) 0.244 (6.19) 0.008 (0.20) 0.224 (5.69) 0.003 (0.08) 0.021 (0.53) 0.011 (0.28) 0.050 (1.27) TYP Lead Coplanarity : 0.004 (0.10) MAX NOTE All dimensions are in inches (millimeters) ©2005 1 HCPL0600, HCPL0601, HCPL0611, HCPL0630, HCPL0631, HCPL0661 Rev. 1.0.1 SEATING PLANE
