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HCF4520
DUAL UP-COUNTERS
1/12October 2002 MEDIUM SPEED OPERATION :
6MHz (Typ.) at 10V POSITIVE -OR NEGATIVE- EDGE
TRIGGERING SYNCHRONOUS INTERNAL CARRY
PROPAGATION QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONHCF4520B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4520B, a Dual Binary Up Counter, consists of
two identical, internal 4-stage counters. The
counter stages are D-type Flip-Flops having
interchangeable Clock and Enable lines for
incrementing on either the positive-going or
negative going transitions. For single-unit
operations the Enable input is maintained High
and the counter advances on each positive going
transition of the Clock. The counters are cleared
by high levels on their Reset lines. The counter
can be cascaded in the ripple mode by connecting
Q4 to the enable input of the subsequent counter
while the clock input of the latter is held low.
HCF4520BDUAL BINARY UP COUNTER
PIN CONNECTION
ORDER CODES
HCF4520B2/12
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
FUNCTIONAL DIAGRAM
TRUTH TABLE X : Don’t Care
HCF4520B3/12
LOGIC DIAGRAM
TIMING CHART
HCF4520B4/12
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF4520B5/12
DC SPECIFICATIONS The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
