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HCF4044
QUAD NAND 3-STATE R-S LATCH
1/10September 2003 QUIESCENT CURRENT SPECIFIED UP TO
20V 3-LEVEL OUTPUTS WITH COMMON
OUTPUT ENABLE SEPARATE SET AND RESET INPUT FOR
EACH LATCH 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT= 100nA (MAX)AT VDD =18VTA= 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OFB SERIES CMOS
DEVICES"
DESCRIPTIONThe HCF4044Bisa monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology availablein DIP and SOP packages.
The HCF4044Bisa quad cross-coupled 3-state
CMOS NAND latch.
Each latch hasa separateQ output and individual
SET and RESET input. The Q outputs are
controlledbya common ENABLE input.A logic "1" "high"on the ENABLE inputs connects the latch
statesto theQ outputs.A logic "0"or "low"on the
ENABLE input disconnects the latch states from
the Q outputs, resulting in an open circuit
condition on the Q outputs. The open circuit
feature allows common bussingof the outputs.
HCF4044BQUAD NAND 3-STATE R-S LATCH
PIN CONNECTION
ORDER CODES
HCF4044B2/10
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE: Don’t Care;Z= High Impedance; Latched:No change
FUNCTIONAL DIAGRAM
HCF4044B3/10
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not implied.
All voltage valuesare referredto VSSpin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF4044B4/10
SPECIFICATIONSThe Noise Marginfor both"1"and"0" levelis:1V min. with VDD=5V,2V min. with VDD=10V, 2.5V min. with VDD=15V
HCF4044B5/10
DYNAMIC ELECTRICAL CHARACTERISTICS(T amb= 25°C,CL= 50pF,RL= 200KΩ,tr=tf =20ns)
(*) Typical temperature coefficientforall VDD valueis 0.3%/°C.
TEST CIRCUIT= 50pFor equivalent (includesjig and probe capacitance) =200KΩ =ZOUTof pulse generator (typically 50Ω)
HCF4044B6/10
WAVEFORM1: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
