HCF4035 ,4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTERHCF4035B 4 STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER ■ 4 STAGE CLOCKED SHIFT OPERATION■ SYNCHR ..
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HCF4035
4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER
1/11September 2001 4 STAGE CLOCKED SHIFT OPERATION SYNCHRONOUS PARALLEL ENTRY ON
ALL 4 STAGES JK INPUTS ON FIRST STAGE ASYNCHRONOUS TRUE/COMPLEMENT
CONTROL ON ALL OUTPUTS STATIC FLIP-FLOP OPERATION;
MASTER-SLAVE CONFIGURATION BUFFERED INPUTS AND OUTPUTS HIGH SPEED 12MHz (Typ.) at VDD = 10V QUIESCENT CURRENT SPECIF. UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONThe HCF4035B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
This device is a four stage clocked signal serial
register with provision for synchronous
PARALLEL inputs to each stage and SERIAL
inputs to the first stage via JK logic. Register
stages 2, 3, and 4 are coupled in a serial D flip-flop
configuration when the register is in the serial
mode (PARALLEL/SERIAL control low). Parallel
entry into each register stage is permitted when
the PARALLEL/SERIAL control is high. In the
parallel or serial mode information is transferred
on positive clock transitions. When the TRUE/
COMPLEMENT control is high, the true contents
of the register are available at the output
terminals. When the TRUE/COMPLEMENT
control is low, the outputs are the complements of
the data in the register. The TRUE/
COMPLEMENT control functions asynchronously
with respect to the CLOCK signal. JK input logic is
provided on the first stage SERIAL input to
minimize logic requirements particularly in
counting and sequence generation applications.
With JK inputs connected together, the first stage
becomes a D flip-flop. An asynchronous common
RESET is also provided.
HCF4035B 4 STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER
PIN CONNECTION
ORDER CODES
HCF4035B2/11
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
FUNCTIONAL DIAGRAM
TRUTH TABLE X : Don’t Care
HCF4035B3/11
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF4035B4/11
DC SPECIFICATIONS The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
HCF4035B5/11
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
