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HCF4029
PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE
1/12September 2002 MEDIUM SPEED OPERATION : 8MHz (Typ.)
at CL = 50pF and VDD - VSS = 10V MULTI-PACKAGE PARALLEL CLOCKING
FOR SYNCHRONOUS HIGH SPEED
OUTPUT RESPONSE OR RIPPLE
CLOCKING FOR SLOW CLOCK INPUT RISE
AND FALL TIMES "PRESET ENABLE" AND INDIVIDUAL "JAM"
INPUTS PROVIDED BINARY OR DECADE UP/DOWN
COUNTING BCD OUTPUTS IN DECADE MODE QUIESCENT CURRENT SPECIF. UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS INPUT LEAKAGE CURRENT I = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONHCF4029B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4029B consists of a four stage binary or
BCD-decade up/down counter with provisions for
look ahead carry in both counting modes. The
inputs consist of a single CLOCK, CARRY IN
(CLOCK ENABLE), BINARY/DECADE, UP/
DOWN, PRESET ENABLE, and four individual
JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT
signal are provided as outputs. A high PRESET
ENABLE signal allows information on the JAM
INPUTS to preset the counter to any state
asynchronously with the clock. A low on each JAM
line, when the PRESET-ENABLE signal is high,
resets the counter to its zero count. The counter
advances one count at the positive transition of
the clock when the CARRY-IN and PRESET
ENABLE signals are low. Advancement is
inhibited when the CARRY-IN or PRESET
ENABLE signals are high. The CARRY-OUT
HCF4029BPRESETTABLE UP/DOWN COUNTER
BINARY OR BCD DECADE
PIN CONNECTION
ORDER CODES
HCF4029B2/12
signal is normally high and the counter reaches its
maximum count in the UP mode or the minimum
count in the DOWN mode provided the CARRY-IN
signal is low. The CARRY-IN signal in the low
state can thus be considered a CLOCK ENABLE.
The CARRY-IN terminal must be connected to
VSS when not in use. Binary counting is
accomplished when the BINARY/DECODE input
is high; the counter counts in the decade mode
when the BINARY/DECADE input is low. The
counter counts Up when to UP/DOWN INPUT is
high, and Down when the UP/DOWN INPUT is
low. Multiple packages can be connected in either
a parallel clocking or a ripple clocking
arrangement. Parallel clocking provides
synchronous control and, hence, a faster
response from all counting outputs. Ripple
clocking allows for longer clock input rise and fall
times.
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
FUNCTIONAL DIAGRAM
HCF4029B3/12
TRUTH TABLE X: Don’t Care
TRUTH TABLE
LOGIC DIAGRAM
HCF4029B4/12
TIMING CHART - Binary Mode
TIMING CHART - Decade Mode
HCF4029B5/12
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF4029B6/12
DC SPECIFICATIONS The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
