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HCF4022
OCTAL COUNTER WITH 8 DECODED OUTPUTS
1/11September 2001 MEDIUM SPEED OPERATION :
10 MHz (Typ.) at VDD = 10V FULLY STATIC OPERATION STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO
20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONThe HCF4022B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4022B is 4-stage Johnson counter
having 8 decoded outputs. Inputs include a
CLOCK, a RESET, and a CLOCK INHIBIT signal.
Schmitt trigger action in the clock input circuit
provides pulse shaping that allows unlimited clock
input pulse rise and fall times. This counter is
advanced one count at the positive clock signal
transition if the CLOCK INHIBIT signal is low.
Counter advanced via the clock line is inhibited
when the CLOCK INHIBIT signal is high. A high
RESET signal clears the counter to its zero count.
Use of the Johnson decade-counter configuration
permits high speed operation, 2-input decimal
decode gating and spike-free decoded outputs.
Anti-lock gating is provided, thus assuring proper
counting sequence. The decoded outputs are
normally low and go high only at their respective
decoded time slot. Each decoded output remains
high for one full clock cycle. A CARRY - OUT
signal completes one cycle every 8 clock input
cycles and is used to ripple-clock the succeeding
device in a multi-device counting chain.
HCF4022BOCTAL COUNTER WITH 8 DECODED OUTPUTS
PIN CONNECTION
ORDER CODES
HCF4022B2/11
INPUT EQUIVALENT CIRCUIT
FUNCTIONAL DIAGRAM
PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
Qn : No Change
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
HCF4022B3/11
TIMING CHART
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF4022B4/11
DC SPECIFICATIONS The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
HCF4022B5/11
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) Measured with respect to carry out line.
HCF4022B6/11
TYPICAL APPLICATIONSDIVIDE BY N COUNTER(N WITH
DECODED OUTPUTS
When the Nth decoded output is reached (Nth
clock pulse) the S-R flip-flop (constructed from two
NOR gates of the HCF4001B) generates a reset
pulse which clears the HCF4022B to its zero
count. At this time, if the Nth decoded output is
greater than or equal to 6, the COUT line goes high
to clock the next HCF4022B counter section. The
"0" decoded output also goes high at this time.
Coincidence of the clock low and decoded "0"
output high resets the S-R flip-flop to enable the
HCF4022B. If the Nth decoded output is less than
6, the COUT line will not go high and, therefore,
cannot be used. In this case "0" decoded output
may be used to perform the clocking function for
the next counter.
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
