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HCF4021
8-STAGE STATIC SHIFT REGISTERS
1/11September 2001 MEDIUM SPEED OPERATION : 12 MHz
(Typ.) CLOCK RATE AT VDD - VSS = 10V FULLY STATIC OPERATION 8 MASTER-SLAVE FLIP-FLOPS PLUS
OUTPUT BUFFERING AND CONTROL
GATING QUIESCENT CURRENT SPECIFIED UP TO
20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT I = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONThe HCF4021B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
This device is an 8-stage parallel or serial input/
serial output register having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a single
SERIAL data input, and individual parallel "JAM"
inputs to each register stage. Each register stage
is a D-type, master-slave flip-flop in addition to an
output from stage 8, "Q" outputs are also available
from stages 6 and 7. Serial entry is synchronous
with the clock but parallel entry is asynchronous.
In this device, entry is controlled by the
PARALLEL/SERIAL CONTROL input. When the
PARALLEL/SERIAL CONTROL input is low, data
is serially shifted into the 8-stage register
synchronously with the positive transition of he
clock line. When the PARALLEL/SERIAL
CONTROL input is high, data is jammed into the
8-stage register via the parallel input lines and
synchronous with the positive transition of the
clock line, the CLOCK input of the internal stage is
"forced" when asynchronous parallel entry is
made. Register expansion using multiple package
is permitted.
HCF4021BASYNCHRONOUS PARALLEL IN OR SYNCHRONOUS
SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER
PIN CONNECTION
ORDER CODES
HCF4021B2/11
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM
HCF4021B3/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF4021B4/11
DC SPECIFICATIONS The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
HCF4021B5/11
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time and the fixed propagation delay
of the output of the driving stage of the estimated capacitive load.
HCF4021B6/11
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : PROPAGATION DELAY TIMES, CLOCK PULSE WIDTH (f=1MHz; 50% duty cycle)
