HCF40193 ,PRESETTABLE UP/DOWN COUNTERS (DUAL CLOCK WITH RESET) BINARY TYPEHCF40193BPRESETTABLE UP/DOWN COUNTERS(DUAL CLOCK WITH RESET) BINARY TYPE ■ INDIVIDUAL CLOCK LINES ..
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HCF40193
PRESETTABLE UP/DOWN COUNTERS (DUAL CLOCK WITH RESET) BINARY TYPE
1/12September 2002 INDIVIDUAL CLOCK LINES FOR COUNTING
UP OR COUNTING DOWN SYNCHRONOUS HIGH-SPEED CARRY AND
BORROW PROPAGATION DELAYS FOR
CASCADING ASYNCHRONOUS RESET AND PRESET
CAPABILITY MEDIUM-SPEED OPERATION - fCL = 8MHz
(typ.) AT 10 V STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONHCF40193B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40193B Presettable Binary Up/Down Counter
consists of 4 synchronously clocked, GATED "D"
type flip-flops connected as a counter. The inputs
consist of four individual jam lines, a PRESET
ENABLE control, individual CLOCK UP and
CLOCK DOWN signals and a master RESET.
Four buffered Q signal outputs as well as CARRY
and BORROW outputs for multiple-stage counting
schemes are provided. The counter is cleared so
that all outputs are in a low state by a high on the
RESET line. A RESET is accomplished
asynchronously with the clock. Each output is
individually programmable asynchronously with
the clock to the level on the corresponding jam
input when the PRESET ENABLE control is low.
The counter counts up one count on the positive
clock edge of the CLOCK UP signal provided the
CLOCK DOWN line is high. The counter counts
down one count on the positive clock edge of the
CLOCK DOWN signal provided the CLOCK UP
line is high. The CARRY and BORROW signals
are high when the counter counts up or down. The
CARRY signal goes low one-half clock cycle after
the counter reaches its maximum count in the
count-up mode. The BORROW signal goes low
HCF40193BPRESETTABLE UP/DOWN COUNTERS
(DUAL CLOCK WITH RESET) BINARY TYPE
PIN CONNECTION
ORDER CODES
HCF40193B2/12
one-half clock cycle after the counter reaches its
minimum count in the count-down mode. The
cascading of multiple packages is easily
accomplished without the need for additional
external circuitry by tying the BORROW and
CARRY outputs to the CLOCK DOWN and
CLOCK UP inputs, respectively, of the following
package.
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
FUNCTIONAL DIAGRAM
HCF40193B3/12
LOGIC DIAGRAM
TRUTH TABLE (X) : Don’t Care
HCF40193B4/12
TIMING DIAGRAM
INTERNAL LOGIG OF FLIP-FLOP
HCF40193B5/12
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
