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HCF40182BEY
LOOK-AHEAD CARRY GENERATOR
1/10September 2002 GENERATES HIGH-SPEED CARRY
ACROSS FOUR ADDERS OR ADDER
GROUPS HIGH-SPEED OPERATIONAL: t PHL = t PLH =
100 ns (typ.) AT VDD = 10V CASCADABLE FOR FAST CARRIES OVER
N BITS DESIGNED FOR USE WITH HCF40181B
ALU STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO
20V INPUT LEAKAGE CURRENT I = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONHCF40182B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
He is a high speed look-ahead carry generator
capable of anticipating a carry across four binary
adders or adder groups. HCF40182B is
cascadable to perform full look-ahead across n-bit
adders. Carry propagate-carry, and
generate-carry functions are provided as
enumerated in the terminal designation below.
HCF40182B, when used in conjunction with the
HCF40181B arithmetic logic unit (ALU), provides
full high-speed look-ahead carry capability for up
to n-bit words. Each HCF40182B generates the
look-ahead (anticipated carry) across a group of
four ALUs. In addition, other HCF40182Bs may be
emplayed to anticipate the carry across sections
of four look-ahead blocks up to n-bits.
HCF40182BLOOK-AHEAD CARRY GENERATOR
PIN CONNECTION
ORDER CODES
HCF40182B2/10
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
FUNCTIONAL DIAGRAM
TRUTH TABLESFOR G OUTPUT
FOR P OUTPUT
HCF40182B3/10
FOR Cn+x OUTPUT
FOR Cn+y OUTPUT
FOR Cn+z OUTPUT
X : Don’t Care
Cn+x = G0+P0Cn
Cn+y = G1+P1G0+P1P0Cn
Cn+z = G2+P2G1+P2P1G0+P2P1P0Cn
G = G3+G3+P3G2+P3P2G1+P3P2P1G0
P = P3P2P1P0
or
Cn+x = Y0+(X0+Cn)
Cn+y = Y1+[X1+Y0(X0+Cn)]
Cn+z = Y2+{X2+Y1[X1+Y0(X0+Cn)]}
G = Y3+(X3+Y2)(X3+X2+Y1)(X3+X2+X1+Y0)
P = X3+X2+X1+X0
HCF40182B4/10
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF40182B5/10
DC SPECIFICATIONS The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
HCF40182B6/10
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
