HCF4018 ,PRESETTABLE DIVIDE-BY-N COUNTERHCF4018BPRESETTABLE DIVIDE-BY-N COUNTER ■ MEDIUM SPEED OPERATION 10 MHz (Typ.) at V - V = 10VDD ..
HCF40181BEY ,4-BIT ARITHMETIC LOGIC UNITHCC/HCF40181B4-BIT ARITHMETIC LOGIC UNIT. FULL LOOK-AHEAD CARRY FOR SPEEDOPERATIONS ON LONG WORDS. ..
HCF40182BEY ,LOOK-AHEAD CARRY GENERATORHCF40182BLOOK-AHEAD CARRY GENERATOR ■ GENERATES HIGH-SPEED CARRY ACROSS FOUR ADDERS OR ADDER GROUP ..
HCF4018BEY ,PRESETTABLE DIVIDE-BY-N COUNTERHCF4018BPRESETTABLE DIVIDE-BY-N COUNTER ■ MEDIUM SPEED OPERATION 10 MHz (Typ.) at V - V = 10VDD ..
HCF40193 ,PRESETTABLE UP/DOWN COUNTERS (DUAL CLOCK WITH RESET) BINARY TYPEHCF40193BPRESETTABLE UP/DOWN COUNTERS(DUAL CLOCK WITH RESET) BINARY TYPE ■ INDIVIDUAL CLOCK LINES ..
HCF4019BM1 ,QUAD AND/OR SELECT GATEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
HD64F2144TE20 , Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
HD64F2144TE20 , Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
HD64F2148ATE20 , Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
HD64F2148ATE20 , Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
HD64F2148FA20 , Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
HD64F2328VTE25 , Old Company Name in Catalogs and Other Documents
HCF4018
PRESETTABLE DIVIDE-BY-N COUNTER
1/11September 2001 MEDIUM SPEED OPERATION 10 MHz (Typ.)
at VDD - VSS= 10V FULLY STATIC OPERATION STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO
20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONThe HCF4018B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4018B consist of 5 Johnson counter
stages, buffered Q outputs from each stage, and
counter preset control gating. CLOCK, RESET,
DATA, PRESET ENABLE, and 5 individual JAM
inputs are provided. Divide by 10, 8, 6, 4 or 2
counter configuration can be implemented by
feeding the Q5, Q4, Q3, Q2, Q1 signals,
respectively, back to the data input.
Divide-by-9, 7, 5, or 3 counter configurations can
be implemented by the use of a HCF4011B gate
package to properly gate the feedback connection
to the DATA input. Divide-by-functions greater
than 10 can be achieved by use of multiple
HCF4018B units. The counter is advanced one
count at the positive clock signalstransition.
Schmitt trigger action on the clock line permits
unlimited clock rise and fall times. A high RESET
signal clears the counter to an all-zero condition. A
high PRESENT-ENABLE signal allows
information on the JAM inputs to preset the
counter.
Anti-lock gating is provided to assure the proper
counting sequence.
HCF4018BPRESETTABLE DIVIDE-BY-N COUNTER
PIN CONNECTION
ORDER CODES
HCF4018B2/11
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
FUNCTIONAL DIAGRAM
HCF4018B3/11
LOGIC DIAGRAM
TIMING CHART
HCF4018B4/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF4018B5/11
DC SPECIFICATIONS The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
HCF4018B6/11
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) At PRESET ENABLE or JAM inputs
