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HCF4015
DUAL 4-STAGE STATIC SHIFT REGISTER WITH SERIAL INPUT/PARALLEL OUTPUT
1/10September 2002 MEDIUM SPEED OPERATION 12 MHz (Typ.)
CLOCK RATE AT VDD - VSS = 10V FULLY STATIC OPERATION 8 MASTER-SLAVE FLIP-FLOPS PLUS
INPUT AND OUTPUT BUFFERING HIGH NOISE IMMUNITY QUIESCENT CURRENT SPECIFIED UP TO
20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT I = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONHCF4015B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4015B consists of two identical, independent,
4 stage serial-input/parallel-output registers.
Each register has independent CLOCK and
RESET inputs as well as a single serial DATA
input. "Q" outputs are available from each of the
four stages on both registers. All register stages
are D-TYPE, MASTER-SLAVE flip-flops. The
logic level present at the DATA input is transferred
into the first register stage and shifted over one
stage at each positive going clock transition. The
resetting of all stages is accomplished by a high
level on the reset line. It is possible to expand the
register to 8 stages using one HCF4015B
package and to expand to more than 8 stages by
using addition HCF4015Bs.
HCF4015BDUAL 4-STAGE STATIC SHIFT REGISTER WITH
SERIAL INPUT/PARALLEL OUTPUT
PIN CONNECTION
ORDER CODES
HCF4015B2/10
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
FUNCTIONAL DIAGRAM
TRUTH TABLE X : Don’t Care
HCF4015B3/10
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF4015B4/10
DC SPECIFICATIONS The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
HCF4015B5/10
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of the fixed prop-
agation delay at 15 pF and the transmission time of the carry output driving stage of the estimated capacitive load.
HCF4015B6/10
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
