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HCF4013BEY-HCF4013BM1-HCF4013M013TR
DUAL 'D'
1/9September 2001 SET - RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS
STATE INDEFINITELY WITH CLOCK LEVEL
EITHER "HIGH" OR "LOW" MEDIUM SPEED OPERATION 16MHz (TYP.)
CLOCK TOGGLE RATE AT 10V STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO
20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONThe HCF4013B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4013B consists of two identical,
independent data type flip-flops. Each flip-flop has
independent data, set, reset, and clock inputs and
Q and Q outputs. This device can be used for shift
register applications, and, by connecting Q output
to the data input, for counter and toggle
applications. The logic level present at the D input
is transferred to the Q output during the
positive-going transition of the clock pulse. Setting
or resetting is independent of the clock and is
accomplished by a high level on the set or reset
line, respectively
HCF4013BDUAL D-TYPE FLIP FLOP
PIN CONNECTION
ORDER CODES
HCF4013B2/9
INPUT EQUIVALENT CIRCUIT
LOGIC DIAGRAM
PIN DESCRIPTION
TRUTH TABLE X : Don’t Care Δ : Low Level
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF4013B3/9
DC SPECIFICATIONS The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
HCF4013B4/9
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) Input tr, tf = 5ns
(2) If more than unit is cascaded in a parallel clocked application, tr should be made less than or equal to the sum of the fixed propagation
delay time at 15pF and the transition time of the carry output driving stage for the estimated capacitive load.
HCF4013B5/9
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : CLOCK TO Qn, Qn PROPAGATION DELAY TIMES, Dn TO CLOCK SETUP AND
HOLD TIMES, CLOCK MINIMUM PULSE WITDH, MAXIMUM CLOCK FREQUENCY(f=1MHz; 50% duty cycle)
HCF4013B6/9
WAVEFORM 2 : PROPAGATION DELAY TIMES (Qn, Qn TO SET, RESET), MINIMUM PULSE WIDTH
(SET AND RESET) (f=1MHz; 50% duty cycle)
