HAS-1409AKM ,14-bit, 125kHz analog-to-digital converterCHARACTERISTICS' lit-
Himtonics2 dB - 100 . - 80
Ihtermodulation Products2 dB - 100 . - 90
Conve ..
HAS500-S , Current Transducers HAS 50 to 600-S
HAS50-S , Current Transducers HAS 50 to 600-S
HAT1016R-EL-E , Silicon P Channel Power MOSFET High Speed Power Switching
HAT1016R-EL-E , Silicon P Channel Power MOSFET High Speed Power Switching
HAT1020 , Silicon P Channel Power MOS FET High Speed Power Switching
HD6303YF , CMOS MPU
HD6303YF , CMOS MPU
HD6305X2F , CMOS MCU (Microcomputer Unit)
HD6340FP , PTM(Programmble Timer Module)
HD6340FP , PTM(Programmble Timer Module)
HD63484-8 , ADVANCED CRT CONTROLLER (ACRTC)
HAS-1409AKM
14-bit, 125kHz analog-to-digital converter
Cy, ANALOG
DEVICES
14-Bit, 125kHz
Analog-to-Digital Converter
HAS-1409
FEATURES HAS-l409 FUNCTIONAL BLOCK DIAGRAM
"-BhRttsohMon ____________ -
125kHzWordRutos l" -- - ‘"_"""""1l
Internal TratStqtrtd-Httid cft'lli'ilir-i-- mama I
40-Hn DIP "JJJll"-ir- mm I
APPLICATIONS ANALOG E I
FDMITDM TransrttuMpttuatrs mm I mm” - q w ,
CAT/NMR Scanners l L - CONVERTER , l
POM Systems I concemn A "ltll% J. till. . 'd't' it WI
Digital Audio l l d ttm 'il" ', OUTPUT
General Instrumentation I HAS-1409 l
L -i--..-------------r--------------.-...r.- .1
GENERAL DESCRIPTION
The HAS-l409KM, HAS-1409LM, and HAS-l409AKM hybrid 86,5KH2 tMkHz
A/D converters offer designers performance characteristics which ( I
have never before been available. ---20dB
Now, for the first time, high resolution and high speed come
together in a hybrid package which includes an internal track-and-
hold. The HAS-l409 units have resolutions of 14 bits, are capable
of word rates up to 125kHz, and are complete with track-and-hold;
all of these features are housed in a single 40-pin DIP package
which dissipates only two watts.
The HAS-l409KM and HAS-l409LM both include internal
clocks, which allow the converters to be operated at any word
rate from dc through 120kHi; the HAS-1409AKM is designed
for applications which use an external system clock whose fre-
quency establishes the user's optimum word rate, up to
125kHz.
The HAS-l409 A/D has been characterized with a companion
D/A converter, the HDD-1409KM, to emphasize the superior
ac performance needed for use in Frequency Division Multiplex/
Time Division Multiplex (FDM/TDM) transmultiplexer systems.
Although specifically designed for these kinds of applications, it
can also be used for other digital signal processing such as Computer
Aided Tomography (CAT) and Nuclear Magnetic Resonance
(NMR) smnners, and Pulse Code Modulation (PCM).
Conventional data converters often display errors at midscale
which make them inadequate for use in the types of systems
cited above. The unique Digitally Corrected Subranging technique
pioneered by Analog Devices, used with other proprietary tech-
niques, virtually cancels midscale errors in the HAS-l409, thereby
eliminating a major source of system errors.
llIl‘l‘ Illllll lllllll \Ill‘lllm
',,cr..ra, _s---1tr0drs
10dB/div Vertical; 5kHz/div Horizontal
Spectrum analyzer shows extremely low
intermodulation (IM) products of
back-to-back HA S- 1409 A/D and HDD- 1409 WA
The logic outputs are TTL-compatible and are presented as 14
bits of parallel data. Buffer output registers and a 3-state format
provide dual advantages of good drive and bus compatibility.
ANALOG-TO-DIGITAL CONVERTERS 3-587
SPEC I Fl CATI OIG (typical @ +25°c with numinal power supplies unless unlerwise naked)
Unit: HAS-MMKM HAS-NMAKM HAS-MMLM
RESOLUTION (FS-- Full Scale) Bits (%FS) 14 (0.006) * .
LSBWEIGHT wV 610or 122i,deimndingoainputmtge . *
ACCURACY
Linearity g de %PS t l/ZLSB 0.006 . .
Morwtouicity 'C Guaranteed 0 to + 85 . .
Nonlinearity vs. Temperature pmeC S . .
Win Error %FS 1 . .
Gain vs. Temperature pmeC 20 . .
DYNAMIC CHARACTERISTICS‘
Humonics2 dB - 100 . - 80
Intermodulation Ptoducts2 dB - l00 . - 90
Conversion Rate kHz 120012 guaranteed) 1253 120(112 guaranteed)
Aperture Time (Delay) n: 50 . .
Signal to Noise Ratio (SNRY dB 80 . .
Noise Power Ratio(NPR)’ dB 68 * 65
Tnnxient Responses us 8 A 2
Overvrtltage Recovety '" 8 . 6
Input Bandwidth
Small Signal, SdB' kHz 200 * 800
umSignal, 3dB" kHz 200 . 300
Idle Noise&Hi"' dB - 104 . .
ANALOG INPUT
Voltage Ranges V, FS t S; t10 . .
Overvtrltage V, mu , 20 . .
Input Type Bipolar . .
Impedance kn S; 10 . '
Offset
Initial-Set u Factory mV (max) 2 (10) . .
vs. Temperature wwc loo * *
ENCODECOMMAN D INPUT"
Logic Levels, TTLA2mpatible V "o'' " 0 w + 0.4 * .
"P'- +2.4to +5 . *
Impedance TTL hood: 1 * *
Min nu SO I Clock .
Max n: T-so" Period .
Frequency kHz T dc to 125 Synchronous to .
External Clock
CLOCK INPUT
Logic Levels, TTLA3orttpatihte V
N/A “0"20to +0.4 N/A
N/A "I"-- +2.4to+5 N/A
Impedance TH. lands N/A 2 N/A
Frequency" ‘MHz, mu N/A 4.5 N/A
DIGITAL OUTPUT
Format Bits " Parallel; 3 State . .
Logic Levels, TTTAkestpstitsle V "O" - 0 to + 0.4 * *
''t'%r+2.4to+5 . .
Drive TTT. Leads , . '
Time Skew n3, mu 20 . .
Coding Offset Binary (MSB); . *
2'eckrmplement (m) * .
POWER REQUIREMENTS
+15V Y. 5% mA 20 I .
- 15V 2 5% mA 40 * .
+ w 2 5% mA 220 200 .
Power Dissipation W(max) 2.00.4) l.8(2.2) *
TEMPERATTIRE RANGE"
Operating 'C - 25 to + 85 . .
Storage 'C - 55 to + ISO . *
THERMAL RESISTANCE"
Imon to Air, hs
(Free Air) W 25 . .
Junction to Case, on W 16 * *
MEAN TIME BETWEEN FAILURES“
(MTBF) Hours 4.15 x ltr * .
PACKAGE OPTION”
M40 HAS. 1409KM HAS. 1409AKM HAS- 1409LM
For applications asistmce, phone Compmer Labs Division " (919) 668-95 I 1
NOTES 'With rs mb.‘ . . . .
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3-588 ANALOG-TO-DIGITAL CONVERTERS
Theory of Operation - M$-140il
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect-
ed; however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
HAS-l409 PIN DESIGNATION
rm mummntu Pm mummuxm Pttl ruucnomxmama
, :wvmrut 21 DtGtrAkGROUND " DIGITALOROUND
2 :SVINPUT 22 autumn " mum!
a ANALOGGROUND " tWrmMsttt " iWrimasm
. MGtTALGROUND 24 W " im
s +sv 25 m 25 B-fr'
a +sv " W " "im"
1 MC " ritTg " W
a MC " 3m " W
a +sv " EN-ABWgRmtMstut " EttAt_ggIMstut
" MGRALGR0UN0 an CLOCK so ENC-ODE
u W433.) 3t m 3t ENCODE
" Brr‘tltLSB) 32 45V " +sv
" ‘sn‘ia " DIGITALGROUND " DiGrTALGRtWND
" W12 " -tw " -15v
" igrr-t, as nsv " nsv
" run so DIGITALGROUND " DrGiTALGROUND
" trrC9 " ANALOGGROUND 37 ANALOGGROUND
" tTfCg " ANA1.0GGR0UND u ANALOGGROUND
" 3-177 " MW " ow
" nmmtenouuo 40 ANALOGGROUND " ANALOGGROUND
ALL + SV PINS ARE CONNECTED TOGETHER INTERNALLV ts. O. 9. 32.3Sl. MUST ALSO BE
CONNECTED TOGETHER EXTERNALLV CLOSE TO CASE.
ALL ANALOG GROUND PINS ARE CONNECTED T0tWTt4ERiNTERNALLY u. " M.MI.
ALI. DIGITAL GROUND PINS ARE CONNECTED TOGETHER INTERNALLY [4, 10, 20,21. " MO,
FOR BEST PERFORMANCE. ANALOG GROUND AND DIGITAL GROUND PINS MUST ALI. BE
CONNECTED TOGETHER AND TO GWERNALLV AS CLOSE TOTHE CASE AS POSSIBLE.
HAS-l409KM/HAS-I409AKM TIMING
Refer to the block diagram of the HAS-l409AKM AID
converter.
In the HAS-l409KM, and HAS-I409LM, signals applied to the
timing circuits will be different from those shown. For them,
these signals will be ENCODE or ENCODE.
In all units, the analog input to be digitized is applied first to a
track-and-hold (T/H) circuit, which is normally in “me ",
following all changes in analog as they occur since the T/H is
operating as a buffer amplifier.
Refer to Figure 1, the timing diagram for the HAS-I409KM
and HAS-l409LM A/D converters.
MIN WIDTH I tithtt
MAX WIDTH " T-50m
(T - ENCODE CLOCK PERIOD)
e-A---,
ENCODE PULSE #t PULSE "
GROUNDED) Was 2 "ps----
ENCODE
(ENCODE I PULSE " I I PULSE" I I I
TO + 5V)
l--, A "ps--- l--, , "--
DATA DATA VALID
OUTPUT (PULSE #1 I
Gus , thttps----
DATA VALID
[PULSE #2)
Figure 1. HAS-1409KM and HAS- 1409LM A/D Timing
Diagram
ANALOG- TO-DIGITAL CONVERTERS 3-589
The user determines the point " which digitizing is to be done
by applying an external TTL-compatible signal to the timing
circuits; this causes the T/H to switch from the "track" mode to
the "hold" mode. In the HAS-l409KM and HAS-I409LM, this
"track" to "hold" transition can be accomplished with either
positive triggering or negative triggering. As shown, positive-edge
triggering is done with an ENCODE command and ENCODE
connected to ground. Negative-edge triggering is accomplished
with an ENCODE signal and ENCODE connected to + 5V.
The HAS-I409KM and HAS-I409LM return to "track" auto-
matically approximately Sits after the encode command.
Output data will be valid after a nominal delay of 8ps from the
leading edge of the encode command. Strobing the output data
into external circuits might best be accomplished by using a
square-wave signal for the encode command and using its negative-
going trailing edge as a time reference for the strobing action.
Outpnt data will not yet be valid when that trailing edge occurs,
but the edge can be used " a known reference point for measuring
the 8p.s conversion time.
Internal timing circuits within the HAS-1409 generate the nec-
essary control and timing pulses to operate the unit at a word
rate of 112kHz. This rate is based on:
KM/LM: The internal clocks are adjusted at the factory
for this conversion rate.
AKM: The HAS-1409AKM divides the external clock
frequency of 4.032MHz by a factor of 36:1 and
provides 14 bits of parallel data at the lleHz
word rate established by this ratio. The lleHz
cited in this example is the minimum guaranteed
word rate of the HAS-l409, and is a sample rate
commonly used in transmultipiexer applications.
(See FDM/TDM Transmultiplexers section of
data sheet).
Figure 2 shows the timing relationship of the HAS-I409AKM
ND converter signals when the converter is being operated
from an external clock.
CLOCK PULSE ll CLOCK WISE I "
CLOCK Jr
ENOOOE
OUTPUT I i
CLOCK CLOCK
PULSE WISE
(or A371 lo! #38)
- -1 com" I
200!!! MAX
DATA CHANGING
Figure 2. HAS-1409AKM Nil Timing Diagram (External
Clock Operating at 4. 032MHz}
As shown, the leading edge of the negative-going ENCODE
pulse supplied by the user should occur from 0 to 100ns after
the leading edge of the clock pulse which is shown (for purposes
of illustrating timing relationships) " Clock Pulse #1. The
trailing edge of this pulse should occur from 0 to 100ns after the
leading edge of the next clock pulse (designated here " Clock
Pulse #2).
3-590 ANALOG-TO-DIGITAL CONVERTERS
The output data associated with the preceding clock pulse and
ENCODE pulse' will be valid within 200ns of the leading edge
ofClockPulse#l. DamassociatedwithClockPulse#lwillbe
valid within 200ns of the leading edge of Clock Pulse #37.
When the HAS-I409AKM is operated hum a 4.032MHz clock,
the trailing edge of the ENCODE pulse could be used to determine
when the output data will be strobed into external circuits.
The ENCODE pulse is used to insure output data will remain
in synchronization with the clock pulses. Using the leading edge
of the first ENCODE as a reference, the HAS-l409AKM goes
into "track" after 21 clock pulses (on Clock Pulse #22); and
goes into "hold" after 34 clocks (Clock Pulse #35).
THEORY OF OPERATION
With the exception of the difference in input signals applied to
the timing circuits, all converters operate in essentially the same
Referring again to the block diagram, the timing circuits " rem”
the analog signal at the output of the track-and-hold. This held
value is applied to an A/D converter in the HAS-l409, and the
same value is applied to one input of a difference amplifier.
The output of the internal AID converter is digitized and applied
to a D/A converter which is 14-bit accurate and optimized for ac
applications; the A/D output is also applied to correction logic
circuits.
The D/A output is applied to the second input of the difference
amplifier, which generates an error signal indicative of the dif-.
ference between the "held" analog input and a digital represen-
tation of that signal. This residue signal is then converted and is
also applied to the digital correction circuits.
The correction circuits combine the two bytes to compensate for
nonlinearities and other circuit errors. Basically, the information
contained in the second byte is used as the Least Significant
Bits (LSBs) and determines what corrective action is needed for
the first byte (the MSBs) to insure its accuracy.
APPLICATIONSI'I'ESTING
For FDM/TDM applications, the analog input frequency applied
to the HAS-l409 will be in the frequency band of 60-10sz;
the combined HAS-l409/HDD-l409 performance parameters
have been optimized for this use.
Refer to Figure 3 HAS-l409 Basic Interface.
IWASS mr" turue
CE nmlc AND >Mrr
TANYALW CAPACimRS
CLOSE TO CASE
Figure 3. HA S- 1409 Basic Interface
As shown, the anlog input is applied to Pin 1 or Pin 2, depending
on the amplitude of the signal to be digitized. A TTL-compatible
pulse is applied as ENCODE; and another TTL-compatible
signal is applied " the clock. As indicated earlier in the timing
diagram, these signals must be synchronous.
The ENABLE HIGH and ENABLE LOW signals applied to
Pins 29 and 11 control the state of the digital outputs. The
TI'L ENABLE HIGH signal affects BIT 1 (MSB), Bit 1 CMM),
and Bits 2-6; the ENABLE LOW affects Bits 7-14. When
ENABLE HIGH and/or ENABLE LOW inputs are connected
HAS-1409
to ground or logical "O", their corresponding bit outputs will be
present. When they are connected to a logical "I" voltage, their
associated bit outputs will be open.
The 3-state TI'L digital output signals will be available at Pins
12-19 and Pins 22-28. Pins 34 and 35 are used for -15V and
+ ISV supplies; + w is applied to several places-Pins 5, 6, 9,
32, and 39 (all pins should be connected). All three supplies
should be bypassed as close as possible to the hybrid case. For
best performance, all ANALOG GROUND and DIGITAL
GROUND pins must be connected together and to ground ex-
ternally; this should also be done close to the case.
Refer to Figure 4 Basic Test Setup.
unnam-
-- W158 -e HA5!“
”-140! T" IAWASS -
etoex GiRiiR LOAD GATE
Figure 4. Basic Test Setup
The HAS-l409 AID converter has been characterized for per-
formance in a back-to-back hook-up with the HDD-1409 D/A
converter. The analog signal to be digitized and reconstructed is
applied to this test arrangement through a bandpass filter of
60kHz-108kH2; the resulting analog output is also passed through
the same kind of Mer.
CLOCK and ENCODE signals are generated in synchronization
with one another and are timed for correct interaction with the
STROBE and GATE signals applied to the BIA. Because of the
back-to-back configuration of the two converters, the performance
tests are indicative of the baseline characteristics of both units.
Refer to Figure 5 Intermodulation (Total Harmonic) Distortion
Test Circuit.
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CLOCK {MW LOAD GATE
Figure 5. Intermodulation (Total Harmonic) Distortion Test
Circuit
Harmonics levels and intermodulation (IM) products are measured
in the same way to assure optimum performance in FDMrrDM
system applications. The purpose of the testing is to insure that
"beat" frequencies generated by the interaction of two signals
are sufficiently suppressed to avoid interfering with the carrier
frequencies and masking their information contents.
In these tests, the HAS-l409 is operated at a lleHz word rate,
established by the external 4.032MHi clock. Two pure sinewave
signals at frequencies of 9lkHz and 86.5kHz are applied to a
summation amplifier at precise levels 21d11 below the rms value
of a full-scale sinewave.
These particular input frequencies are selected on the basis that
their interaction with one another will generate second and
third-order harmonics and IM products which are easily distin-
guished and measurable. As in any sampling scheme, these
signals are "folded" back into the passband of interest and their
amplitudes are a measure of ND and D/A performance.
The output of the summation amplifier is applied through the
60-108km filter, digitized, reconstructed, and tefilteted. Typi-
cally, the levels of harmonics and intermodulation products are
- lOOdB.
Refer to Figure 6 Noise Power Ratio Test Circuit.
mucus: ”1m"! “JMN- MARCONI NOISE
GENERATOR - MASS - HAS-IM ”00.1.0! .I BANDPASS r. REC£NER
mull HLTEI HLVEI Tramc
”IWINI 70'
coo: ENCOOE LOAD GATE
Figure 6. Noise Power Ratio Test Circuit
Noise Power Ratio (NPR) is a critical measure of AID and D/A
performance for FDM/TDM systems and the method of measuring
this ratio must replicate the conditions which are present when
the units are operating as a part of those systems. In this test,
also, the HAS-l409 is operating at 112kHz word rates.
White noise in the frequency band of 60kHz to 108kHz is applied
to the A/D, and the total power which is present in a narrow
"slot" at a frequency of 70kHi is computed. A narrow bandstop
filter whose center frequency is 70kHz is then switched in, and
the total power remaining in the "slot" is computed. The ratio
of these two readings is the NPR and the result for the HAS-l409
is typically 68dB. CAUTION: The high-performance character-
istics of the HAS-l409 stress the measurement capabilities of
most NPR test sets.
Refer to Figure 7 Idle Noise Test Circuit. In this test, a spectrally-
pure sinewave of 84kHz is applied through a filter to the HAS.. 1409/
HDD-1409 combination at a level of --41dB. An encode rate of
lleI-Iz is used; the combination of input frequency and encode
rate cancels all harmonics, leaving only the fundamental input
frequency and noise components.
SPECTMLLV'UIE sum”: J ”loll”! MON“
Mk“: - IANM'ASS .q “A54“! upoqun - IANDPASS - SPECTRUM
-6NA, FILTER "t/ FILER ANMVZEI
Figure 7. Idle Noise Test Circuit
The results of digitizing and reconstructing this signal are examined
with a spectrum analyzer to determine the level of noise compo-
nents contributed by the converters. Acceptable performance
will show average idle noise components to be at -104dB when
using a 1kHz-reso1ution filter.
ANALOG-TO-DIGITAL CONVERTERS 3-591
