GTLP6C817 ,Low Drive GTLP/LVTTL 1:6 Clock DriverFeaturesThe GTLP6C817 is a low drive clock driver that provides
GTLP6C817
Low Drive GTLP/LVTTL 1:6 Clock Driver
GTLP6C817 Low Drive GTLP/LVTTL 1:6 Clock Driver June 1999 Revised December 2000 GTLP6C817 Low Drive GTLP/LVTTL 1:6 Clock Driver General Description Features The GTLP6C817 is a low drive clock driver that providesInterface between LVTTL and GTLP logic levels TTL to GTLP signal level translation (and vice versa). TheDesigned with edge rate control circuitry to reduce out- device provides a high speed interface between cards put noise on the GTLP port operating at TTL logic levels and a backplane operating at V pin provides external supply reference voltage for REF GTLP logic levels. High speed backplane operation is a receiver threshold adjustibility direct result of GTLP’s reduced output swing (<1V), Special PVT compensation circuitry to provide consis- reduced input threshold levels and output edge rate con- tent performance over variations of process, supply volt- trol. The edge rate control minimizes bus settling time. age and temperature GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standardTTL compatible driver and control inputs JESD8-3. Designed using Fairchild advanced CMOS technology Fairchild’s GTLP has internal edge-rate control and is pro- Bushold data inputs on A port to eliminate the need for cess, voltage, and temperature (PVT) compensated. Its external pull-up resistors for unused inputs function is similar to BTL and GTL but with different output Power up/down and power off high impedance for live levels and receiver threshold. GTLP output LOW level is insertion typically less than 0.5V, the output level HIGH is 1.5V and 5V over voltage tolerance on LVTTL ports the receiver threshold is 1.0V. Open drain on GTLP to support wired-or connection A Port source/sink −12mA/+12mA B Port sink +40mA 1:6 fanout clock driver for TTL port 1:2 fanout clock driver for GTLP port Ordering Code: Order Number Package Number Package Description GTLP6C817MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device is also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Connection Diagram Pin Names Description TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively) OEB Output Enable (Active LOW) GTLP Port (TTL Levels) OEA Output Enable (Active LOW) TTL Port (TTL Levels) V .GNDT LVTTL Output Supplies (3V) CCT V Internal Circuitry V (5V) CC CC GNDG OBn GTLP Output Grounds V Voltage Reference Input REF OA0–OA5 TTL Buffered Clock Outputs OB0–OB1 GTLP Buffered Clock Outputs © 2000 DS500246
