GTLP6C816 ,GTLP/TTL 1:6 Clock DriverFeaturesThe GTLP6C816 is a clock driver that provides TTL to
GTLP6C816
GTLP/TTL 1:6 Clock Driver
GTLP6C816 GTLP/TTL 1:6 Clock Driver June 1998 Revised December 2000 GTLP6C816 GTLP/TTL 1:6 Clock Driver General Description Features The GTLP6C816 is a clock driver that provides TTL toInterface between LVTTL and GTLP logic levels GTLP signal level translation (and vice versa). The deviceDesigned with edge rate control circuitry to reduce out- provides a high speed interface between cards operating at put noise on the GTLP port TTL logic levels and a backplane operating at GTLP logic V pin provides external supply reference voltage for REF levels. High speed backplane operation is a direct result of receiver threshold adjustibility GTLP’s reduced output swing (<1V), reduced input thresh- Special PVT compensation circuitry to provide consis- old levels and output edge rate control. The edge rate con- tent performance over variations of precess, supply volt- trol minimizes bus settling time. GTLP is a Fairchild age and temperature Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3.TTL compatible driver and control inputs Fairchild’s GTLP has internal edge-rate control and is pro-Designed using Fairchild advanced CMOS technology cess, voltage, and temperature (PVT) compensated. Its Bushold data inputs on A port to eliminate the need for function is similar to BTL and GTL but with different output external pull-up resistors for unused inputs levels and receiver threshold. GTLP output LOW level is Power up/down and power off high impedance for live typically less than 0.5V, the output level HIGH is 1.5V and insertion the receiver threshold is 1.0V. 5V over voltage tolerance on LVTTL ports Open drain on GTLP to support wired-or connection A Port source/sink −24mA/+24mA B Port sink +50mA 1:6 fanout clock driver for TTL port 1:2 fanout clock driver for GTLP port Ordering Code: Order Number Package Number Package Description GTLP6C816MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Connection Diagram Pin Names Description TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively) OEB Output Enable (Active LOW) GTLP Port (TTL Levels) OEA Output Enable (Active LOW) TTL Port (TTL Levels) V .GNDT TTL Output Supplies (5V) CCT V Internal Circuitry V (5V) CC CC GNDG OBn GTLP Output Grounds V Voltage Reference Input REF OA0–OA5 TTL Buffered Clock Outputs OB0–OB1 GTLP Buffered Clock Outputs © 2000 DS500129
