GTLP2T152M ,2-Bit LVTTL/GTLP TransceiverFeaturesThe GTLP2T152 is a 2-bit transceiver that provides LVTTL-
GTLP2T152M-GTLP2T152MX
2-Bit LVTTL/GTLP Transceiver
GTLP2T152 2-Bit LVTTL/GTLP Transceiver June 2001 Revised February 2002 GTLP2T152 2-Bit LVTTL/GTLP Transceiver General Description Features The GTLP2T152 is a 2-bit transceiver that provides LVTTL-Bidirectional interface between GTLP and LVTTL logic to-GTLP signal level translation. Data directional control is levels handled with a transmit/receive pin. High-speed backplaneDesigned with edge rate control circuitry to reduce out- operation is a direct result of GTLP’s reduced output swing put noise on the GTLP port (<1V), reduced input threshold levels and output edge rate V pin provides external supply reference voltage for REF control. The edge rate control minimizes bus-settling time. receiver threshold adjustibility GTLP is a Fairchild Semiconductor derivative of the Gun- Special PVT compensation circuitry to provide consis- ning Transistor logic (GTL) JEDEC standard JESD8-3. tent performance over variations of process, supply volt- Fairchild’s GTLP has internal edge-rate control and is pro- age and temperature cess, voltage and temperature compensated. GTLP’s I/O TTL compatible driver and control inputs structure is similar to GTL and BTL but offers different out- put levels and receiver threshold. Typical GTLP output volt-Designed using Fairchild advanced BiCMOS technology age levels are: V = 0.5V, V = 1.5V, and V = 1V. OL OH REFBushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs Power up/down and power off high impedance for live insertion Open drain on GTLP to support wired-or connection Flow through pinout optimizes PCB layout A Port source/sink −24mA/+24mA B Port sink +50mA Ordering Code: Order Number Package Number Package Description GTLP2T152M M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TUBE] GTLP2T152MX M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TAPE and REEL] GTLP2T152K8X MAB08A 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide (Preliminary) [TAPE and REEL] Pin Descriptions Connection Diagrams US8 Pin Names Description T/R LVTTL Direction Control (Receive Direction is Active LOW) V , GND, V Device Supplies CC REF A A Port LVTTL Input/Output n B B Port GTLP Input/Output n SOIC © 2002 DS500486
