GTLP17T616MTD ,17-Bit LVTTL/GTLP Bus Transceiver with Buffered ClockGTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered ClockJanuary 2000Revised December 2000GT ..
GTLP18T612 ,18-Bit LVTTL/GTLP Universal Bus TransceiverGTLP18T612 18-Bit LVTTL/GTLP Universal Bus TransceiverMay 1999Revised July 2002GTLP18T61218-Bit LVT ..
GTLP18T612MEA ,18-Bit LVTTL/GTLP Universal Bus TransceiverFeaturesThe GTLP18T612 is an 18-bit universal bus transceiver
GTLP17T616MTD
17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock January 2000 Revised December 2000 GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock General Description Features The GTLP17T616 is a 17-bit registered bus transceiverBidirectional interface between GTLP and LVTTL logic that provides LVTTL to GTLP signal level translation. It levels allows for transparent, latched and clocked modes of dataDesigned with edge rate control circuitry to reduce out- flow and provides a buffered GTLP (CLKOUT) clock output put noise on the GTLP port from the LVTTL CLKAB. The device provides a high speed V pin provides external supply reference voltage for REF interface between cards operating at LVTTL logic levels receiver threshold adjustibility and a backplane operating at GTLP logic levels. High Special PVT compensation circuitry to provide consis- speed backplane operation is a direct result of GTLP’s tent performance over variations of process, supply volt- reduced output swing (<1V), reduced input threshold levels age and temperature and output edge rate control. The edge rate control mini- mizes bus settling time. GTLP is a Fairchild SemiconductorTTL compatible driver and control inputs derivative of the Gunning Transistor logic (GTL) JEDEC Designed using Fairchild advanced BiCMOS technology standard JESD8-3. Bushold data inputs on A port to eliminate the need for Fairchild's GTLP has internal edge-rate control and is Pro- external pull-up resistors for unused inputs cess, Voltage, and Temperature (PVT) compensated. Its Power up/down and power off high impedance for live function is similar to BTL or GTL but with different output insertion levels and receiver thresholds. GTLP output LOW level is Open drain on GTLP to support wired-or connection typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.Flow through pinout optimizes PCB layout D-type flip-flop, latch and transparent data paths A Port source/sink −24mA/+24mA B Port sink +50mA GTLP buffered CLKAB signal available (CLKOUT) Ordering Code: Order Number Package Number Package Description GTLP17T616MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide GTLP17T616MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2000 DS500327
