GTLP16T1655MTD ,16-Bit LVTTL/GTLP Universal Bus TransceiverFeaturesThe GTLP16T1655 is a 16-bit universal bus transceiver
GTLP16T1655MTD-GTLP16T1655MTDX
16-Bit LVTTL/GTLP Universal Bus Transceiver
GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls August 1998 Revised January 2005 GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls General Description Features The GTLP16T1655 is a 16-bit universal bus transceiverBidirectional interface between GTLP and LVTTL logic that provides LVTTL to GTLP signal level translation. It levels allows for transparent, latched and clocked modes of dataVariable edge rate control pin to select desired edge rate transfer. The device provides a high speed interface on the GTLP backplane (V ) ERC between cards operating at LVTTL logic levels and a back- V pin provides external supply reference voltage for REF plane operating at GTLP logic levels. High speed back- receiver threshold adjustibility plane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and outputSpecial PVT compensation circuitry to provide consis- edge rate control. The edge rate control minimizes bus set- tent performance over variations of process, supply volt- tling time. GTLP is a Fairchild Semiconductor derivative of age and temperature the Gunning Transceiver Logic (GTL) JEDEC standardTTL compatible driver and control inputs JESD8-3. Designed using Fairchild advanced BiCMOS technology Fairchild’s GTLP has internal edge-rate control and is pro- Bushold data inputs on A port to eliminate the need for cess, voltage, and temperature (PVT) compensated. Its external pull-up resistors for unused inputs function is similar to BTL and GTL but with different output Power up/down and power off high impedance for live levels and receiver threshold. GTLP output LOW level is insertion typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.Open drain on GTLP to support wired-or connection Flow through pinout optimizes PCB layout D-type flip-flop, latch and transparent data paths A Port source/sink −24mA/+24mA B Port sink +100mA Partitioned as two 8-bit transceivers with individual latch timing and output control but with a common clock External pin to pre-condition I/O capacitance to high state (V ) CCBIAS Ordering Code: Order Number Package Number Package Description GTLP16T1655MTD MTD64 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2005 DS500172
