GTLP16617 ,17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered ClockFeaturesThe GTLP16617 is a 17-bit registered synchronous bus
GTLP16617
17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
GTLP16617 17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock June 1997 Revised December 2000 GTLP16617 17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock General Description Features The GTLP16617 is a 17-bit registered synchronous busBidirectional interface between GTLP and TTL logic transceiver that provides TTL to GTLP signal level transla- levels tion. It allows for transparent, latched and clocked modesDesigned with edge rate control circuitry to reduce of data flow and provides a buffered GTLP (CLKOUT) output noise on the GTLP port clock output from the TTL CLKAB. The device provides a V pin provides external supply reference voltage for REF high speed interface between cards operating at TTL logic receiver threshold adjustibility levels and a backplane operating at GTLP logic levels. Special PVT compensation circuitry to provide High speed backplane operation is a direct result of consistent performance over variations of process, GTLP’s reduced output swing (<1V), reduced input thresh- supply voltage and temperature old levels and output edge rate control. The edge rate con- trol minimizes bus settling time. GTLP is a FairchildTTL compatible driver and control inputs Semiconductor derivative of the Gunning Transceiver logic Designed using Fairchild advanced CMOS technology (GTL) JEDEC standard JESD8-3. Bushold data inputs on the A port eliminates the need Fairchild’s GTLP has internal edge-rate control and is pro- for external pull-up resistors on unused inputs. cess, voltage, and temperature (PVT) compensated. Its Power up/down and power off high impedance for live function is similar to BTL and GTL but with different output insertion levels and receiver threshold. GTLP output LOW level is 5 V tolerant inputs and outputs on the LVTTL port typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.Open drain on GTLP to support wired-or connection Flow through pinout optimizes PCB layout D-type flip-flop, latch and transparent data paths A Port source/sink −32 mA/+32 mA GTLP Buffered CLKAB signal available (CLKOUT) Ordering Code: Order Number Package Number Package Description GTLP16617MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide GTLP16617MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 DS500031
