FST32211 ,40/48-Bit Bus SwitchFST32211 40/48-Bit Bus SwitchApril 2001Revised July 2002FST3221140/48-Bit Bus Switch
FST32211G ,40/48-Bit Bus SwitchFST32211 40/48-Bit Bus SwitchApril 2001Revised July 2002FST3221140/48-Bit Bus Switch
FST32211GX ,40/48-Bit Bus SwitchFST32211 40/48-Bit Bus SwitchApril 2001Revised July 2002FST3221140/48-Bit Bus Switch
FST32253 ,Dual 4:1 Multiplexer/Demultiplexer Bus Switch with 25-Ohm Series Resistor in OutputsFeaturesThe Fairchild Switch FST32253 is a dual 4:1 high-speed
FST32211
40/48-Bit Bus Switch
FST32211 40/48-Bit Bus Switch April 2001 Revised July 2002 FST32211 40/48-Bit Bus Switch General Description Features The Fairchild Switch FST32211 provides up to 48-bits of � 4Ω switch connection between two ports high-speed CMOS TTL-compatible bus switching. The low � Minimal propagation delay through the switch On Resistance of the switch allows inputs to be connected � Low l CC to outputs without adding propagation delay or generating � Zero bounce in flow-through mode additional ground bounce noise. � Control inputs compatible with TTL level The device can be organized as four 12-bit, two 24-bit, or one 48-bit bus switch. When routed as a 40-bit bus switch, � Packaged in plastic Fine Pitch Ball Grid Array (FBGA) the device can be organized as four 10-bit, two 20-bit or one 40-bit bus switch. When OE is LOW, the switch is ON 1 and Port 1A is connected to Port 1B. When OE is LOW, 2 the switch is ON and Port 2A is connected to Port 2B. When OE is LOW, the switch is ON and Port 3A is con- 3 nected to Port 3B. When OE is LOW, the switch is ON and 4 Port 4A is connected to Port 4B. When OE , OE , OE , or 1 2 3 OE are HIGH, a high impedance state exists between the 4 A and B Ports. Ordering Code: Order Number Package Number Package Description FST32211G BGA114A 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1)(Note 2) Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Diagram © 2002 DS500404
