FQD3P50 ,500V P-Channel MOSFETAugust 2000TMQFET QFET QFET QFETFQD3P50 / FQU3P50500V P-Channel MOSFET
FQD3P50TF ,500V P-Channel QFETAugust 2000TMQFET QFET QFET QFETFQD3P50 / FQU3P50500V P-Channel MOSFET
FQD3P50TM ,500V P-Channel QFETGeneral DescriptionThese P-Channel enhancement mode power field effect
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FQD3P50
500V P-Channel MOSFET
August 2000 TM QFET QFET QFET QFET FQD3P50 / FQU3P50 500V P-Channel MOSFET General Description These P-Channel enhancement mode power field effect Features transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. • -2.1A, -500V, R = 4.9Ω @V = -10 V DS(on) GS This advanced technology has been especially tailored to • Low gate charge ( typical 18 nC) minimize on-state resistance, provide superior switching • Low Crss ( typical 9.5 pF) performance, and withstand high energy pulse in the • Fast switching avalanche and commutation mode. These devices are well • 100% avalanche tested suited for electronic lamp ballast based on complimentary • Improved dv/dt capability half bridge. S !!!!!!!! D ●●●●●●●● ●●●● G!!!!!!!! ●●●● ▶▶▶▶▶▶▶▶ ▲▲▲▲▲▲▲▲ ●●●●●●●● D-PAK I-PAK G S FQD Series G FQU Series D S !!!! !!!! D Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter FQD3P50 / FQU3P50 Units V Drain-Source Voltage -500 V DSS I - Continuous (T = 25°C) Drain Current -2.1 A D C - Continuous (T = 100°C) -1.33 A C I (Note 1) Drain Current - Pulsed -8.4 A DM V Gate-Source Voltage ± 30 V GSS E (Note 2) Single Pulsed Avalanche Energy 250 mJ AS I Avalanche Current (Note 1) -2.1 A AR E (Note 1) Repetitive Avalanche Energy 5.0 mJ AR dv/dt Peak Diode Recovery dv/dt (Note 3) -4.5 V/ns Power Dissipation (T = 25°C) * 2.5 W P A D Power Dissipation (T = 25°C) 50 W C - Derate above 25°C 0.4 W/°C T , T Operating and Storage Temperature Range -55 to +150 °C J STG Maximum lead temperature for soldering purposes, T 300 °C L 1/8" from case for 5 seconds Thermal Characteristics Symbol Parameter Typ Max Units R Thermal Resistance, Junction-to-Case -- 2.5 °C/W θJC R Thermal Resistance, Junction-to-Ambient * -- 50 °C/W θJA R Thermal Resistance, Junction-to-Ambient -- 110 °C/W θJA * When mounted on the minimum pad size recommended (PCB Mount) ©2000 Fairchild Semiconductor International Rev. A, August 2000 FQD3P50 / FQU3P50
