FQD13N10 ,100V N-Channel MOSFETFeaturesThese N-Channel enhancement mode power field effect 10A, 100V, R = 0.18Ω @V = 10 VDS(on) ..
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FQD13N10
100V N-Channel MOSFET
FQD13N10 / FQU13N10 January 2001 TM QFET QFET QFET QFET FQD13N10 / FQU13N10 100V N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect 10A, 100V, R = 0.18Ω @V = 10 V DS(on) GS transistors are produced using Fairchild’s proprietary, Low gate charge ( typical 12 nC) planar stripe, DMOS technology. Low Crss ( typical 20 pF) This advanced technology has been especially tailored to Fast switching minimize on-state resistance, provide superior switching 100% avalanche tested performance, and withstand high energy pulse in the Improved dv/dt capability avalanche and commutation mode. These devices are well suited for low voltage applications such as audio amplifier, high efficiency switching DC/DC converters, and DC motor control. D D ! ! "" !!"" "" G! ! "" D-PAK I-PAK G S G FQD Series FQU Series D S ! ! S Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter FQD13N10 / FQU13N10 Units V Drain-Source Voltage 100 V DSS I - Continuous (T = 25°C) Drain Current 10 A D C - Continuous (T = 100°C) 6.3 A C I (Note 1) Drain Current - Pulsed 40 A DM V Gate-Source Voltage ± 25 V GSS E (Note 2) Single Pulsed Avalanche Energy 95 mJ AS I Avalanche Current (Note 1) 10 A AR E (Note 1) Repetitive Avalanche Energy 4.0 mJ AR dv/dt Peak Diode Recovery dv/dt (Note 3) 6.0 V/ns Power Dissipation (T = 25°C) * 2.5 W P A D Power Dissipation (T = 25°C) 40 W C - Derate above 25°C 0.32 W/°C T , T Operating and Storage Temperature Range -55 to +150 °C J STG Maximum lead temperature for soldering purposes, T 300 °C L 1/8" from case for 5 seconds Thermal Characteristics Symbol Parameter Typ Max Units R Thermal Resistance, Junction-to-Case -- 3.13 °C/W θJC R Thermal Resistance, Junction-to-Ambient * -- 50 °C/W θJA R Thermal Resistance, Junction-to-Ambient -- 110 °C/W θJA * When mounted on the minimum pad size recommended (PCB Mount) ©2000 Fairchild Semiconductor International Rev. A1, January 2001