FQB1P50TM ,500V P-Channel QFETFQB1P50 / FQI1P50December 2000TMQFET QFET QFET QFETFQB1P50 / FQI1P50500V P-Channel MOSFET
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FQB1P50TM
500V P-Channel QFET
FQB1P50 / FQI1P50 December 2000 TM QFET QFET QFET QFET FQB1P50 / FQI1P50 500V P-Channel MOSFET General Description Features These P-Channel enhancement mode power field effect -1.5A, -500V, R = 10.5Ω @V = -10 V DS(on) GS transistors are produced using Fairchild’s proprietary, Low gate charge ( typical 11 nC) planar stripe, DMOS technology. Low Crss ( typical 6.0 pF) This advanced technology is especially tailored to minimize Fast switching on-state resistance, provide superior switching 100% avalanche tested performance, and withstand a high energy pulse in the Improved dv/dt capability avalanche and commutation modes. These devices are well suited for electronic lamp ballasts based on the complementary half bridge topology. S D !!!!!!!! ●●●● ●●●● G!!!!!!!! ●●●●●●●● ▶▶▶▶ ▶▶▶▶ ▲▲▲▲▲▲▲▲ ●●●● ●●●● G S 2 2 D -PAK I -PAK G D S FQB Series FQI Series !!!!!!!! D Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter FQB1P50 / FQI1P50 Units V Drain-Source Voltage -500 V DSS I - Continuous (T = 25°C) Drain Current -1.5 A D C - Continuous (T = 100°C) -0.95 A C I (Note 1) Drain Current - Pulsed -6.0 A DM V Gate-Source Voltage ± 30 V GSS E (Note 2) Single Pulsed Avalanche Energy 110 mJ AS I Avalanche Current (Note 1) -1.5 A AR E (Note 1) Repetitive Avalanche Energy 6.3 mJ AR dv/dt Peak Diode Recovery dv/dt (Note 3) -4.5 V/ns Power Dissipation (T = 25°C) * 3.13 W P A D Power Dissipation (T = 25°C) 63 W C - Derate above 25°C 0.51 W/°C T , T Operating and Storage Temperature Range -55 to +150 °C J STG Maximum lead temperature for soldering purposes, T 300 °C L 1/8” from case for 5 seconds Thermal Characteristics Symbol Parameter Typ Max Units R Thermal Resistance, Junction-to-Case -- 1.98 °C/W θJC R Thermal Resistance, Junction-to-Ambient * -- 40 °C/W θJA R Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W θJA * When mounted on the minimum pad size recommended (PCB Mount) ©2000 Fairchild Semiconductor International Rev. A2, December 2000
