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FM24C128
128K--Bit Standard 2-Wire Bus Interface Serial EEPROM
FM24C128 – 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM December 2001 FM24C128 – 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM General Description Features FM24C128 is a 128Kbit CMOS non-volatile serial EEPROM � Extended operating voltage: 2.5V to 5.5V organized as 16K x 8 bit memory. This device confirms to � Up to 400 KHz clock frequency at 2.5V to 5.5V Extended IIC 2-wire protocol that allows accessing of memory in � Low power consumption excess of 16Kbit on an IIC bus. This serial communication protocol —0.5mA active current typical uses a Clock signal (SCL) and a Data signal (SDA) to synchro- —10µA standby current typical nously clock data between a master (e.g. a microcontroller) and a —1µA standby current typical (L version) slave (EEPROM). FM24C128 is designed to minimize pin count —0.1µA standby current typical (LZ version) and simplify PC board layout requirements. � Schmitt trigger inputs FM24C128 offers hardware write protection where by the entire � 64 byte page write mode memory array can be write protected by connecting WP pin to V . CC � Self timed write cycle (6ms max) The entire memory then becomes unalterable until the WP pin is switched to V . SS � Hardware Write Protection for the entire array � Endurance: up to 100K data changes “LZ” and “L” versions of FM24C128 offer very low standby current making them suitable for low power applications. This device is � Data Retention: Greater than 40 years offered in SO, TSSOP and DIP packages. � Packages: 8-Pin DIP, 8-Pin SO and 8-Pin TSSOP Fairchild EEPROMs are designed and tested for applications � Temperature range requiring high endurance, high reliability and low power consump- —Commercial: 0°C to +70°C tion. —Industrial (E): -40°C to +85°C —Automotive (V): -40°C to +125°C Block Diagram V SS WRITE V CC LOCKOUT H.V. GENERATION WP TIMING &CONTROL START SDA STOP LOGIC CONTROL LOGIC SLAVE ADDRESS 2 E PROM REGISTER & ARRAY COMPARATOR XDEC SCL A2 WORD A1 ADDRESS A0 COUNTER R/W YDEC CK D OUT DATA REGISTER D IN 1 © 2001 FM24C128 Rev. D
