FIN1048 ,3.3V LVDS 4-Bit Flow-Through High Speed Differential ReceiverFeaturesThis quad receiver is designed for high speed interconnect
FIN1048
3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver
FIN1048 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver September 2001 Revised September 2001 FIN1048 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver General Description Features This quad receiver is designed for high speed interconnectGreater than 400Mbs data rate utilizing Low Voltage Differential Signaling (LVDS) technol-Flow-through pinout simplifies PCB layout ogy. The receiver translates LVDS levels, with a typical dif- 3.3V power supply operation ferential input threshold of 100mV, to LVTTL signal levels. 0.4ns maximum differential pulse skew LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed2.5ns maximum propagation delay transfer of clock and data.Low power dissipation The FIN1048 can be paired with its companion driver, thePower-Off protection FIN1047, or any other LVDS driver. Fail safe protection for open-circuit, shorted and termi- nated conditions Meets or exceeds the TIA/EIA-644 LVDS standard Pin compatible with equivalent RS-422 and LVPECL devices 16-Lead SOIC and TSSOP packages save space Ordering Code: Order Number Package Number Package Description FIN1048M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow FIN1048MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Name Description R , R , R , R LVTTL Data Outputs OUT1 OUT2 OUT3 OUT4 R , R , R , R Non-Inverting LVDS Inputs IN1+ IN2+ IN3+ IN4+ R , R , R , R Inverting LVDS Inputs IN1− IN2− IN3− IN4− EN Driver Enable Pin EN Inverting Driver Enable Pin V Power Supply CC GND Ground Function Table Inputs Outputs EN EN R R R IN+ OUT− OUT HL or Open H L H HL or Open L H L H L or Open Fail Safe Condition H XH X X Z L or Open X X X Z H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance Fail Safe = Open, Shorted, Terminated © 2001 DS500588
