FIN1032MX ,3.3V LVDS 4-Bit High Speed Differential ReceiverElectrical CharacteristicsOver supply voltage and operating temperature ranges, unless otherwise sp ..
FIN1032MX ,3.3V LVDS 4-Bit High Speed Differential ReceiverFeaturesThis quad receiver is designed for high speed interconnect
FIN1032M-FIN1032MTC-FIN1032MTCX-FIN1032MX
3.3V LVDS 4-Bit High Speed Differential Receiver
FIN1032 3.3V LVDS 4-Bit High Speed Differential Receiver August 2001 Revised December 2001 FIN1032 3.3V LVDS 4-Bit High Speed Differential Receiver General Description Features This quad receiver is designed for high speed interconnectGreater than 400Mbs data rate utilizing Low Voltage Differential Signaling (LVDS) technol-3.3V power supply operation ogy. The receiver translates LVDS levels, with a typical dif- 0.4ns maximum differential pulse skew ferential input threshold of 100mV, to LVTTL signal levels. 2.5ns maximum propagation delay LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speedLow power dissipation transfer of clock and data.Power OFF protection The FIN1032 can be paired with its companion driver, theFail safe protection for open-circuit, shorted and termi- FIN1031, or any other Fairchild LVDS driver. nated conditions Meets or exceeds the TIA/EIA-644 LVDS standard Pin compatible with equivalent RS-422 and LVPECL devices 16-Lead SOIC and TSSOP packages save space Ordering Code: Order Number Package Number Package Description FIN1032M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow FIN1032MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Function Table Connection Diagram Inputs Outputs EN EN R R R IN+ OUT− OUT HX H L H HX L H L H X Fail Safe Condition H XL H L H XL L H L X L Fail Safe Condition H LH X Z H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance Fail Safe = Open, Shorted, Terminated Pin Descriptions Pin Name Description R , R , R , R LVTTL Data Outputs OUT1 OUT2 OUT3 OUT4 R , R , R , R Non-Inverting LVDS Inputs IN1+ IN2+ IN3+ IN4+ R , R , R , R Inverting LVDS Inputs IN1− IN2− IN3− IN4− EN Driver Enable Pin EN Inverting Driver Enable Pin V Power Supply CC GND Ground © 2001 DS500508
