FIN1025 ,3.3V LVDS 2-Bit High Speed Differential DriverFeaturesThis dual driver is designed for high speed interconnects
FIN1025
3.3V LVDS 2-Bit High Speed Differential Driver
FIN1025 3.3V LVDS 2-Bit High Speed Differential Driver June 2002 Revised June 2002 FIN1025 3.3V LVDS 2-Bit High Speed Differential Driver General Description Features This dual driver is designed for high speed interconnectsGreater than 400Mbs data rate utilizing Low Voltage Differential Signaling (LVDS) technol-Flow-through pinout simplifies PCB layout ogy. The driver translates LVTTL signal levels to LVDS lev- 3.3V power supply operation els with a typical differential output swing of 350mV which 0.4ns maximum differential pulse skew provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed trans-1.7ns maximum propagation delay fer of clock and data.Low power dissipation The FIN1025 can be paired with its companion receiver,Power-Off protection the FIN1026, or any other LVDS receiver. Meets or exceeds the TIA/EIA-644 LVDS standard 14-Lead TSSOP package saves space Ordering Code: Order Number Package Number Package Description FIN1025MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Name Description D , D , LVTTL Data Inputs IN1 IN2 D , D Non-Inverting Driver Outputs OUT1+ OUT2+ D , D Inverting Driver Outputs OUT1− OUT2− EN Driver Enable Pin EN Inverting Driver Enable Pin V Power Supply CC GND Ground NC No Connect Truth Table Inputs Outputs EN EN D D D IN OUT+ OUT− HL or OPEN H H L HL or OPEN L L H H L or OPEN OPEN L H XH X Z Z L or OPEN X X Z Z H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance © 2002 DS500783
