FIN1019MX ,3.3V LVDS High Speed Differential Driver/ReceiverElectrical Characteristics (Continued)Device CharacteristicsI Power Supply Current Driver Enabled, ..
FIN1019MX ,3.3V LVDS High Speed Differential Driver/ReceiverFIN1019 3.3V LVDS High Speed Differential Driver/ReceiverApril 2001Revised September 2001FIN10193.3 ..
FIN1022 ,2 X 2 LVDS High Speed Crosspoint SwitchFeaturesThis non-blocking 2x2 crosspoint switch has a fully differ-
FIN1019M-FIN1019MTC-FIN1019MTCX-FIN1019MX
3.3V LVDS High Speed Differential Driver/Receiver
FIN1019 3.3V LVDS High Speed Differential Driver/Receiver April 2001 Revised September 2001 FIN1019 3.3V LVDS High Speed Differential Driver/Receiver General Description Features This driver and receiver pair are designed for high speedGreater than 400Mbs data rate interconnects utilizing Low Voltage Differential Signaling3.3V power supply operation (LVDS) technology. The driver translates LVTTL signals to 0.5ns maximum differential pulse skew LVDS levels with a typical differential output swing of 2.5ns maximum propagation delay 350mV and the receiver translates LVDS signals, with a typical differential input threshold of 100mV, into LVTTLLow power dissipation levels. LVDS technology provides low EMI at ultra lowPower-Off protection power dissipation even at high frequencies. This device is 100mV receiver input sensitivity ideal for high speed clock or data transfer. Fail safe protection open-circuit, shorted and terminated conditions Meets or exceeds the TIA/EIA-644 LVDS standard Flow-through pinout simplifies PCB layout 14-Lead SOIC and TSSOP packages save space Ordering Code: Order Number Package Number Package Description FIN1019M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow FIN1019MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Function Table Connection Diagram Inputs Outputs R R RE R IN+ IN− OUT LH L L HL L H XX H Z Fail Safe Condition L H D DE D D IN OUT+ OUT− LH L H Pin Descriptions HH H L XL Z Z Pin Name Description Open−Circuit or Z H L H D LVTTL Data Input IN H = HIGH Logic Level L = LOW Logic Level X = Don’t Care D Non-inverting LVDS Output OUT+ Z = High Impedance Fail Safe = Open, Shorted, Terminated D Inverting LVDS Output OUT− DE Driver Enable (LVTTL, Active HIGH) R Non-Inverting LVDS Input IN+ R Inverting LVDS Input IN− R LVTTL Receiver Output OUT RE Receiver Enable (LVTTL, Active LOW) V Power Supply CC GND Ground NC No Connect © 2001 DS500506
