FIN1018 ,3.3V LVDS 1-Bit High Speed Differential ReceiverFeaturesThis single receiver is designed for high speed intercon-
FIN1018
3.3V LVDS 1-Bit High Speed Differential Receiver
FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver March 2001 Revised April 2002 FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver General Description Features This single receiver is designed for high speed intercon-Greater than 400Mbs data rate nects utilizing Low Voltage Differential Signaling (LVDS)3.3V power supply operation technology. The receiver translates LVDS levels, with a typ- 0.4ns maximum pulse skew ical differential input threshold of 100 mV, to LVTTL signal 2.5ns maximum propagation delay levels. LVDS provides low EMI at ultra low power dissipa- tion even at high frequencies. This device is ideal for highLow power dissipation speed transfer of clock or data.Power-Off protection The FIN1018 can be paired with its companion driver, theFail safe protection for open-circuit, shorted and termi- FIN1017, or with any other LVDS driver. nated conditions Meets or exceeds the TIA/EIA-644 LVDS standard Flow-through pinout simplifies PCB layout 8-Lead SOIC and US-8 packages save space Ordering Code: Order Number Package Number Package Description FIN1018M M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TUBE] FIN1018MX M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TAPE and REEL] FIN1018K8X MAB08A 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide [TAPE and REEL] Pin Descriptions Connection Diagrams Pin Name Description 8-Lead SOIC R LVTTL Data Output OUT R Non-inverting Driver Input IN+ R Inverting Driver Input IN− V Power Supply CC GND Ground NC No Connect Pin Assignment for US-8 Package Function Table Input Outputs R R R IN+ IN− OUT LH L HL H Fail Safe Condition H H = HIGH Logic Level L = LOW Logic Level TOP VIEW Fail Safe = Open, Shorted, Terminated © 2002 DS500502
