FIN1017MX ,3.3V LVDS 1-Bit High Speed Differential DriverFeaturesThis single driver is designed for high speed interconnects
FIN1017K8X-FIN1017M-FIN1017MX
3.3V LVDS 1-Bit High Speed Differential Driver
FIN1017 3.3V LVDS 1-Bit High Speed Differential Driver April 2001 Revised April 2002 FIN1017 3.3V LVDS 1-Bit High Speed Differential Driver General Description Features This single driver is designed for high speed interconnectsGreater than 600Mbs data rate utilizing Low Voltage Differential Signaling (LVDS) technol-3.3V power supply operation ogy. The driver translates LVTTL signal levels to LVDS lev- 0.5ns maximum differential pulse skew els with a typical differential output swing of 350 mV which 1.5ns maximum propagation delay provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed trans-Low power dissipation fer of clock or data.Power-Off protection The FIN1017 can be paired with its companion receiver,Meets or exceeds the TIA/EIA-644 LVDS standard the FIN1018, or with any other LVDS receiver. Flow-through pinout simplifies PCB layout 8-Lead SOIC and US8 packages save space Ordering Code: Order Number Package Number Package Description FIN1017M M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TUBE] FIN1017MX M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TAPE and REEL] FIN1017K8X MAB08A 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide [TAPE and REEL] Connection Diagrams 8-Lead SOIC Pin Assignment for US-8 Package Note: Ground pins 4 and 5 for optimum operation. TOP VIEW Pin Descriptions Function Table Pin Name Description Input Outputs D LVTTL Data Input D D D IN IN OUT+ OUT− D Non-inverting Driver Output OUT+ LL H D Inverting Driver Output HH L OUT− V Power Supply OPEN L H CC GND Ground H = HIGH Logic Level L = LOW Logic Level X = Don’t Care NC No Connect © 2002 DS500500
