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FDG6318PFAIN/a4623avaiDual P-Channel, Digital FET


FDG6318P ,Dual P-Channel, Digital FETFeatures These dual P-Channel logic level enhancement mode • –0.5 A, –20 V. R = 780 mΩ @ V = –4.5 V ..
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FDG6318P
Dual P-Channel, Digital FET
FDG6318P January 2003 FDG6318P Dual P-Channel, Digital FET General Description Features These dual P-Channel logic level enhancement mode • –0.5 A, –20 V. R = 780 mΩ @ V = –4.5 V DS(ON) GS MOSFET are produced using Fairchild Semiconductor’s R = 1200 mΩ @ V = –2.5 V DS(ON) GS advanced PowerTrench process that has been especially tailored to minimize on-state resistance. This device has been designed especially for low voltage • Very low level gate drive requirements allowing direct applications as a replacement for bipolar digital transistors and small signal MOSFETS. operation in 3V circuits (V < 1.5V). GS(th) Applications • Compact industry standard SC70-6 surface mount package • Battery management S G S 1 or 4 6 or 3 D D G 2 or 5 5 or 2 G D G 4 or 1 Pin 1 D 3 or 6 S S SC70-6 The pinouts are symmetrical; pin 1 and pin 4 are interchangeable. o Absolute Maximum Ratings T =25 C unless otherwise noted A Symbol Parameter Ratings Units V Drain-Source Voltage –20 V DSS V Gate-Source Voltage ±12 V GSS ID Drain Current – Continuous (Note 1) –0.5 A – Pulsed –1.8 P Power Dissipation for Single Operation (Note 1) 0.3 W D T , T Operating and Storage Junction Temperature Range –55 to +150 °C J STG Thermal Characteristics R Thermal Resistance, Junction-to-Ambient (Note 1) 415 °C/W θJA Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity .38 FDG6318P 7’’ 8mm 3000 units FDG6318P Rev C (W) 2003
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