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FDG6302P
Dual P-Channel, Digital FET
July 1999 FDG6302P Dual P-Channel, Digital FET General Description Features -25 V, -0.14 A continuous, -0.4 A peak. These dual P-Channel logic level enhancement mode R = 10 W @ V = -4.5 V, field effect transistors are produced using Fairchild's DS(ON) GS proprietary, high cell density, DMOS technology. This R = 13 W @ V = -2.7 V. DS(ON) GS very high density process is especially tailored to Very low level gate drive requirements allowing direct minimize on-state resistance. This device has been operation in 3 V circuits (V < 1.5 V). designed especially for low voltage applications as a GS(th) replacement for bipolar digital transistors and small Gate-Source Zener for ESD ruggedness signal MOSFETs. (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. TM TM SOT-23 SuperSOT -6 SO-8 SC70-6 SuperSOT -8 SOT-223 S2 G2 1 or 4 * 6 or 3 D1 2 or 5 5 or 2 D2 . G1 S1 SC70-6 4 or 1 * 3 or 6 *The pinouts are symmetrical; pin 1 and 4 are interchangeable. Units inside the carrier can be of either orientation and will not affect the functionality of the device. Absolute Maximum Ratings T = 25°C unless otherwise noted A Symbol Parameter FDG6302P Units V Drain-Source Voltage -25 V DSS V Gate-Source Voltage -8 V GSS I Drain/Output Current - Continuous -0.14 A D - Pulsed -0.4 P Maximum Power Dissipation (Note 1) 0.3 W D T ,T Operating and Storage Temperature Range -55 to 150 °C J STG ESD Electrostatic Discharge Rating MIL-STD-883D 6.0 kV Human Body Model (100 pF / 1500 W) THERMAL CHARACTERISTICS R Thermal Resistance, Junction-to-Ambient (Note 1) 415 °C/W qJA FDG6302P Rev.F1 .02
