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FDG6301N_F085
Dual N-Channel Digital FET
FDG6301N_F085 Dual N-Channel, Digital FET March 2009 FDG6301N_F085 Dual N-Channel, Digital FET General Description Features 25 V, 0.22 A continuous, 0.65 A peak. These dual N-Channel logic level enhancement mode R = 4 W @ V = 4.5 V, field effect transistors are produced using Fairchild's DS(ON) GS proprietary, high cell density, DMOS technology. This R = 5 W @ V = 2.7 V. DS(ON) GS very high density process is especially tailored to Very low level gate drive requirements allowing direct minimize on-state resistance. This device has been operation in 3 V circuits (V < 1.5 V). designed especially for low voltage applications as a GS(th) replacement for bipolar digital transistors and small Gate-Source Zener for ESD ruggedness signal MOSFETs. (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. Qualified to AEC Q101 RoHS Compliant TM TM SOT-23 SuperSOT -6 SO-8 SC70-6 SuperSOT -8 SOT-223 S2 1 or 4 * G2 6 or 3 D1 2 or 5 5 or 2 D2 G1 S1 4 or 1 * 3 or 6 SC70-6 *The pinouts are symmetrical; pin 1 and 4 are interchangeable. Units inside the carrier can be of either orientation and will not affect the functionality of the device. Absolute Maximum Ratings T = 25°C unless otherwise noted A Symbol Parameter FDG6301N_F085 Units V Drain-Source Voltage 25 V DSS V Gate-Source Voltage 8 V GSS I Drain/Output Current - Continuous 0.22 A D - Pulsed 0.65 P Maximum Power Dissipation (Note 1) 0.3 W D T ,T Operating and Storage Temperature Range -55 to 150 °C J STG ESD Electrostatic Discharge Rating MIL-STD-883D 6.0 kV Human Body Model(100 pF / 1500 W) THERMAL CHARACTERISTICS R Thermal Resistance, Junction-to-Ambient 415 °C/W qJA ©2009 1 FDG6301N_F085 Rev. A .01
