FDC6320C ,Dual N & P Channel , Digital FETElectrical Characteristics (T = 25 C unless otherwise noted )ASymbol Parameter Conditions Min Typ M ..
FDC6320C ,Dual N & P Channel , Digital FETapplications. Since bias resistors are notGate-Source Zener for ESD ruggedness.required, this dual ..
FDC6321C ,Dual N & P Channel , Digital FETGeneral Description Digital FETDual N & P C321C F O(T = 25 C unless otherwise noted )ATypeV VVo o ..
FDC6322C ,Dual N & P Channel , Digital FETFeaturesThese dual N & P Channel logic level enhancement mode fieldN-Ch 25 V, 0.22 A, R = 5 Ω @ V ..
FDC6323L ,Integrated Load SwitchGeneral Description FDC6323LMarch (TAI V 8 V 1 µ AI V V µ A )V 3 8 VV 8 VV V V VV V VI V 1 ALV 1 ..
FDC6324 ,Integrated Load SwitchFeaturesV=0.2V @ VV, IA, V=1.5 to 8V Integrated Load Switches are produced usingINLV=0.3V @ V=5V, ..
FMS6502 ,8 Input, 6 Output Video Switch Matrix with Output DriversFeatures Description 8 x 6 Crosspoint Switch Matrix The FMS6502 provides eight inputs that can be r ..
FMS6502MTC24 , 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
FMS6502MTC24X , 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
FMS6502MTC24X , 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
FMS6502MTC24X , 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
FMS6502MTC24X , 8-Input, 6-Output Video Switch Matrix with Output Drivers, Input Clamp, and Bias Circuitry
FDC6320C
Dual N & P Channel , Digital FET
October 1997 FDC6320C Dual N & P Channel , Digital FET General Description Features These dual N & P Channel logic level enhancement mode field N-Ch 25 V, 0.22 A, R = 5 W @ V = 2.7 V. DS(ON) GS effec transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density P-Ch 25 V, -0.12 A, R = 13 W @ V = -2.7 V. DS(ON) GS process is especially tailored to minimize on-state resistance. Very low level gate drive requirements allowing direct The device is an improved design especially for low voltage operation in 3 V circuits. V < 1.5 V. applications as a replacement for bipolar digital transistors in GS(th) load switching applications. Since bias resistors are not Gate-Source Zener for ESD ruggedness. required, this dual digital FET can replace several digital >6kV Human Body Model transistors with difference bias resistors. Replace NPN & PNP digital transistors. TM TM SOT-23 SOIC-16 SuperSOT -6 SuperSOT -8 SO-8 SOT-223 4 3 2 5 6 1 o Absolute Maximum Ratings T = 25 C unless other wise noted A Symbol Parameter N-Channel P-Channel Units V , V Drain-Source Voltage, Power Supply Voltage 25 -25 V DSS CC V , V Gate-Source Voltage, 8 -8 V GSS IN I , I Drain/Output Current - Continuous 0.22 -0.12 A D O - Pulsed 0.5 -0.5 Maximum Power Dissipation (Note 1a) 0.9 W P D (Note 1b) 0.7 T ,T Operating and Storage Tempature Ranger -55 to 150 °C J STG ESD Electrostatic Discharge Rating MIL-STD-883D 6 kV Human Body Model (100pf / 1500 Ohm) THERMAL CHARACTERISTICS R Thermal Resistance, Junction-to-Ambient (Note 1a) 140 °C/W qJA R Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W J q C © 1997 FDC6320C.Rev C
