FDB603AL ,N-Channel Logic Level Enhancement Mode Field Effect TransistorFeaturesThese N-Channel logic level enhancement mode power field 33 A, 30 V. R = 0.022 Ω @ V =10 V ..
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FDB603AL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
April 1998 FDP603AL / FDB603AL N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These N-Channel logic level enhancement mode power field 33 A, 30 V. R = 0.022 W @ V =10 V DS(ON) GS effect transistors are produced using Fairchild's proprietary, R = 0.036 W @ V =4.5 V. DS(ON) GS high cell density, DMOS technology. This very high density Critical DC electrical parameters specified at elevated process is especially tailored to minimize on-state temperature. resistance. These devices are particularly suited for low voltage applications such as DC/DC converters and high Rugged internal source-drain diode can eliminate the need efficiency switching circuits where fast switching, low in-line for an external Zener diode transient suppressor. power loss, and resistance to transients are needed. High density cell design for extremely low R . DS(ON) 175°C maximum junction temperature rating. _________________________________________________________________________________ D G S Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter FDP603AL FDB603AL Units V Drain-Source Voltage 30 V DSS V Gate-Source Voltage - Continuous ±20 V GSS I Drain Current - Continuous 33 A D - Pulsed (Note 1) 100 50 W P Total Power Dissipation @ T = 25°C D C Derate above 25°C 0.33 W/°C T ,T Operating and Storage Temperature Range -65 to 175 °C J STG T Maximum lead temperature for soldering purposes, 275 °C L 1/8" from case for 5 seconds THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Case 3 °C/W R qJC Thermal Resistance, Junction-to-Ambient 62.5 °C/W R JA q © 1998 FDP603AL Rev.D
