FC940L ,Low Voltage 1 to 18 Clock Distribution Device with Selectable PECL or LVTTL InputFunctional DescriptionThe FC940L is a 1 to 18 Clock distribution fanout buffer. The output buffers ..
FC940L ,Low Voltage 1 to 18 Clock Distribution Device with Selectable PECL or LVTTL Inputfeatures Typical Pin-to-Pin skew 200 pslow part-to-part and pin-to-pin skews. The outputs of the Ab ..
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FC940L
Low Voltage 1 to 18 Clock Distribution Device with Selectable PECL or LVTTL Input
FC940L Low Voltage 1 to 18 Clock Distribution Device with Selectable PECL or LVTTL Input August 1998 Revised January 1999 FC940L Low Voltage 1 to 18 Clock Distribution Device with Selectable PECL or LVTTL Input General Description Features The FC940L is a 1 to 18 low voltage clock fanout buffer. � Selectable Differential PECL or LVTTL/CMOS inputs The device allows for the selection of either differential � 2.5V/3.3V output V supply operation CC PECL or LVTTL/CMOS input levels. The 18 outputs are � Typical propagation delays 2.5 ns compatible with LVCMOS or LVTTL technology and are � Part-to-Part skew < 900 ps capable of driving 50Ω series or parallel terminated lines. The device has a minimal propagation delay and features � Typical Pin-to-Pin skew 200 ps low part-to-part and pin-to-pin skews. The outputs of the � Ability to drive 50Ω series or parallel terminated trans- device are designed to operate at either 2.5V or 3.3V V . CC mission lines The output transistors have a 20Ω (30Ω) impedance at � Latchup performance exceeds 300 mA 3.3V (2.5V) V . The input and core circuitry operate at CC � ESD performance: 3.3V. Human body model > 2000V The FC940L is fabricated in a high performance BiCMOS Machine model > 200V Process. � Pin compatible to MPC940L � 32 pin TQFP package Ordering Code: Order Number Package Number Package Description FC940LVB VBE32A 32-Lead Thin Quad Flat Package, JEDEC MO-136, 7mm Square Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Assignment for TQFP Pin Names Description PECL_CLK, PECL_CLK Differential PECL Input LVC_CLK LVTTL/CMOS Clock Input SEL Input Selection Pin O[0:17] Low Voltage CMOS Outputs Truth Table Inputs Outputs PECL_CLK LVC_CLK SEL O –O 0 17 LX L L HX L H XL H L XH H H H = High Voltage Level L = Low Voltage Level X = Immaterial © 1999 DS500140.prf
