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ETC5067-ETC5067D/C-ETC5067N/C
SERIAL INTERFACE CODEC/FILTER WITH RECEIVE POWER AMPLIFIER
ETC5064/64-X
ETC5067/67-XSeptember 2003
POWER AMPLIFIER
SERIAL INTERFACE CODEC/FILTER WITH RECEIVE COMPLETE CODEC AND FILTERING SYS-
TEM INCLUDING : Transmit high-pass and low-pass filtering. Receive low-pass filter with sin x/x correction. Active RC noise filter. μ-law or A-law compatible CODER and DE-
CODER. Internal precision voltage reference. Serial I/O interface. Internal auto-zero circuitry. Receive push-pull power amplifiers.. μ-LAW ETC5064. A-LAW ETC5067. MEETS OR EXCEEDS ALL D3/D4 AND CCITT
SPECIFICATIONS.. ± 5 V OPERATION.. LOW OPERATING POWER-TYPICALLY 70 mW. POWER-DOWN STANDBY MODE-TYPICALLY
3 mW. AUTOMATIC POWER DOWN. TTL OR CMOS COMPATIBLE DIGITAL INTER-
FACES. MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY. 0°C TO 70°C OPERATION: ETC5064/67. –40°C TO 85°C OPERATION: ETC5064-X/67-X
DESCRIPTIONThe ETC5064 (μ-law), ETC5067 (A-law) are mono-
lithic PCM CODEC/FILTERS utilizing the A/D and
D/A conversion architecture shown in the Block Dia-
grams and a serial PCM interface. The devices are
fabricated using double-poly CMOS process.
Similar to the ETC505X family, these devices fea-
ture an additional Receive Power Amplifier to pro-
vide push-pull balanced output drive capability. The
receive gain can be adjusted by means of two ex-
ternal resistors for an output level of up to ± 6.6 V
across a balanced 600Ω load.
Also included is an Analog Loopback switch and
TSX output.
1/18
BLOCK DIAGRAM (ETC5064 - ETC5064-X - ETC5067 - ETC5067-X)
PIN CONNECTIONS (Top views)
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X2/18
PIN DESCRIPTION(*) I: Input, O: Output, S: Power Supply.
TRI-STATE is a trademark of National Semiconductor Corp.
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X3/18
FUNCTIONAL DESCRIPTIONPOWER-UP
When power is first applied, power-on reset circuitry
initializes the device and places it into the power-
down mode. All non-essential circuits are deacti-
vated and the DX and VFRO outputs are put in high
impedance states. To power-up the device, a logical
low level or clock must be applied to the
MCLKR/PDN pin and FSX and/or FSR pulses must
be present. Thus 2 power-down control modes are
available. The first is to pull the MCLKR/PDN pin
high; the alternative is to hold both FSX and FSR in-
puts continuously low. The device will power-down
approximately 2 ms after the last FSX pulse. The
TRI-STATE PCM data output, DX, will remain in the
high impedance state until the second FSX pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock
and bit clock should be used for both the transmit
and receive directions. In this mode, a clock must be
applied to MCLKX and the MCLKR/PDN pin can be
used as a power-down control. A low level on
MCLKR/PDN powers up the device and a high level
powers down the device. In either case, MCLKX will
be selected as the master clock for both the transmit
and receive circuits. A bit clock must also be applied
to BCLKX and the BCLR/CLKSEL can be used to se-
lect the proper internal divider for a master clock of
1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544
MHz operation, the device automatically compen-
sates for the 193 rd clock pulse each frame.
With a fixed level on the BCLKR/CKSEL pin, BCLKX
will be selected as the bit clock for both the transmit
and receive directions. Table 1 indicates the fre-
quencies of operation which can be selected, de-
pending on the state of BCLKR/CLKSEL. In this syn-
chronous mode, the bit clock, BCLKX, may be from
64 kHz to 2.048 MHz, but must be synchronous with
MCLKX.
Each FSX pulse begins the encoding cycle and the
PCM data from the previous encode cycle is shift out
of the enabled DX output on the positive edge of
BCLKX. After 8 bit clock periods, the TRISTATE DX
output is returned to a high impedance state. With an
FSR pulse, PCM data is latched via the DR input on
the negative edge of BCLKX (or on BCKLR if running).
FSX and FSR must be synchronous with MCLKX/R.
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and
receive clocks may be applied. MCLKX and MCLKR
must be 2.048 MHz for the ETC5067 or 1.536 MHz,
1.544 MHz for the ETC5064, and need not be syn-
chronous. For best transmission performance, how-
ever, MCLKR should be synchronous with MCLKX,
which is easily achieved by applying only static logic
levels to the MCLKR/PDN pin. This will automatically
connect MCLKX to all internal MCLKR functions (see
pin description). For 1.544 MHz operation, the de-
vice automatically compensates for the 193rd clock
pulse each frame. FSX starts each encoding cycle
and must be synchronous with MCLKX and BCLKX.
FSR starts each decoding cycle and must be syn-
chronous with BCLKR. BCLKR must be a clock, the
logic levels shown in Table 1 are not valid in asyn-
chronous mode. BCLKX and BCLKR may operate
from 64kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The device can utilize either a short frame sync
pulse or a long frame sync pulse. Upon power initiali-
zation, the device assumes a short frame mode. In
this mode, both frame sync pulses. FSX and FSR,
must be one bit clock period long, with timing rela-
tionships specified in figure 2. With FSX high during
a falling edge of BCLKR, the next rising edge of
BCLKX enables the DX TRI-STATE output buffer,
which will output the sign bit. The following seven ris-
ing edges clock out the remaining seven bits, and
the next falling edge disables the DX output. With
FSR high during a falling edge of BCLKR (BCLKX in
synchronous mode), the next falling edge of BCLKR
latches in the sign bit. The following seven falling
edges latch in the seven remaining bits. Both de-
vices may utilize the short frame sync pulse in syn-
chronous or asynchronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync
pulses, FSX and FSR, must be three or more bit clock
periods long, with timing relationships specified in
figure 3. Based on the transmit frame sync FSX, the
device will sense whether short or long frame sync
Table 1: Selection of Master Clock Frequencies.
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X4/18
pulses are being used. For 64 kHz operation, the
frame sync pulses must be kept low for a minimum
of 160 ns (see Fig 1). The DX TRI-STATE output
buffer is enabled with the rising edge of FSX or the
rising edge of BCLKX, whichever comes later, and
the first bit clocked out is the sign bit. The following
seven BCLKX rising edges clock out the remaining
seven bits. The DX output is disabled by the falling
BCLKX edge following the eighth rising edge, or by
FSX going low, whichever comes later. A rising edge
on the receive frame sync pulse, FSR, will cause the
PCM data at DR to be latched in on the next eight
falling edges of BCLKR (BCLKx in synchronous
mode). Both devices may utilize the long frame sync
pulse in synchronous or asynchronous mode.
TRANSMIT SECTION
The transmit section input is an operational amplifier
with provision for gain adjustment using two external
resistors, see figure 4. The low noise and wide band-
width allow gains in excess of 20 dB across the
audio passband to be realized. The op amp drives
a unity gain filter consisting of RC active pre-filter,
followed by an eighth order switched-capacitor
bandpass filter directly drives the encoder sample-
and-hold circuit. The A/D is of companding type ac-
cording to A-law (ETC5067 and ETC5067-X) or μ-
law (ETC5064 and ETC5064-X) coding conven-
tions. A precision voltage reference is trimmed in
manufacturing to provide an input over load (tMAX)
of nominally 2.5V peak (see table of Transmission
Characteristics). The FSX frame sync pulse controls
the sampling of the filer output, and then the succes-
sive-approximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out
through DX at the next FSX pulse. the total encoding
delay will be approximately 165 μs (due to the trans-
mit filter) plus 125μs (due to encoding delay), which
totals 290μs. Any offset voltage due to the filters or
comparator is cancelled by sign bit integration.
RECEIVE SECTION
The receive section consist of an expanding DAC
which drives a fifth order switched-capacitor low
pass filter clocked at 256kHz. The decoder is A-law
(ETC5067 and ETC5067-X) or μ–law (ETC5064
and ETC5064-X) and the 5 th order low pass filter
corrects for the sin x/x attenuation due to the 8kHz
sample and hold. The filter is then followed by a 2
nd order RC active post-filter and power amplifier
capable of driving a 600Ω load to a level of 7.2dBm.
The receive section is unity-gain. Upon the oc-
curence of FSR, the data at the DR input is clocked
in on the falling edge of the next eight BCLKR
(BCKLX) periods. At the end of the decoder time slot,
the decoding cycle begins, and 10μs later the de-
coder DAC output is updated. The total decoder de-
lay is about10μs (decoder up-date) plus 110μs (fil-
ter delay) plus 62.5μs (1/2 frame), which gives ap-
proximately 180μs.
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided
for directly driving a matched line interface trans-
former. The gain of the first power amplifier can be
adjusted to boost the ± 2.5V peak output signal from
the receive filter up ± 3.3V peak into an unbalanced
300Ω load, or ±4.0V into an unbalanced 15kΩ load.
The second power amplifier is internally connected
in unity-gain inverting mode to give 6dB of signal
gain for balanced loads. Maximum power transfer to
a 600Ω subscriber line termination is obtained by
differientially driving a balanced transformer with a2 : 1 turns ratio, as shown in figure 4. A total peak
power of 15.6dBm can be delivered to the load plus
termination. Both power amplifier can be powered
down independently from the PDN input by connect-
ing the VPI input to VBB saving approximately 12
mW of power.
ABSOLUTE MAXIMUM RATINGS
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X5/18
