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ETC5064
POWER AMPLIFIER SERIAL INTERFACE CODEC/FILTERWITH RECEIVE
ETC5064/64-X
ETC5067/67-XPOWER AMPLIFIER
SERIAL INTERFACE CODEC/FILTER WITH RECEIVE
ORDERING NUMBERS:ETC5064FN
ETC5064FN-X
ETC5067FN
ETC5067FN-X
.COMPLETE CODEC AND FILTERING SYS-
TEM INCLUDING: Transmit high-pass and low-pass filtering. Receive low-pass filter withsin x/x correction. Active RC noise filter. μ-lawor A-law compatible CODER and DE-
CODER. Internal precision voltage reference. Serial I/Ointerface. Internal auto-zero circuitry. Receive push-pullpower amplifiers..μ-LAW ETC5064.A-LAW ETC5067.MEETS OR EXCEEDS ALL D3/D4 AND CCITT
SPECIFICATIONS..±5V OPERATION..LOW OPERATING POWER-TYPICALLY70 mW.POWER-DOWN STANDBY MODE-TYPICALLY
3mW .AUTOMATIC POWER DOWN.TTL OR CMOSCOMPATIBLE DIGITAL INTER-
FACES .MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY.0°CTO 70°C OPERATION:ETC5064/67.–40°CTO 85°C OPERATION: ETC5064-X/67-X
DESCRIPTIONTheETC5064 (μ-law), ETC5067 (A-law) are mono-
lithic PCM CODEC/FILTERS utilizing the A/D and
D/Aconversion architectureshownin the BlockDia-
grams anda serial PCM interface. The devices are
fabricated using double-polyCMOS process.
Similarto the ETC505X family, these devices fea-
turean additional Receive Power Amplifierto pro-
vide push-pull balancedoutputdrive capability. The
receive gain canbe adjustedby meansof two ex-
ternal resistorsfor an output levelofupto± 6.6V
acrossa balanced 600Ω load.
Also includedis an Analog Loopback switch and
DIP20(Plastic)N
PLCC20
SO20
ORDERING NUMBERS:ETC5064N
ETC5064N-X
ETC5067N
ETC5067N-X
ORDERING NUMBERS:ETC5064D
ETC5064D-X
ETC5067D
BLOCK DIAGRAM (ETC5064- ETC5064-X- ETC5067- ETC5067-X)
PIN CONNECTIONS (Top views)
DIP20&
SO20
PLCC20
ETC5064- ETC5064-X- ETC5067- ETC5067-X
PIN DESCRIPTION
Name Pin
Type(*) N DescriptionVPO+ O 1 The Non-inverting Outputofthe Receive Power Amplifier
GNDA GND 2 Analog Ground.All signals are referencedto this pin.
VPO- O 3 The Inverting Outputofthe Receive Power Amplifier
VPI I 4 Inverting Inputto the Receive Power Amplifier. Also powers down both
amplifiers when connectedto VBB.
VFRO O 5 Analog Outputof the Receive Filter.
VCC S 6 Positive Power Supply Pin. VCC =+5V ±5%
FSR I 7 Receive Frame Sync Pulse which enable BCLKRto shift PCM data into
DR.FSRisan 8KHz pulse train. See figures1 and2for timing details. I 8 Receive Data Input. PCM datais shifted intoDR following the FSR leading
edge
BCLKR/CLKSEL I 9 Thebit Clock which shifts data intoDR after the FSR leading edge. May
vary from 64KHzto 2.048MHz.
Alternatively, maybea logic input which selects either 1.536MHz/1.544MHz 2.048MHzfor master clockin synchronous mode and BCLKXis used
for both transmit and receive directions (see table1). This input hasan
internal pull-up.
MCKLR/PDN I 10 Receive Master Clock. Mustbe 1.536MHz, 1.544MHzor 2.048MHz. May asynchronous with MCLKX,but shouldbe synchronous with MCLKXfor
best performance. When MCLKRis connected continuously low, MCLKXis
selectedforall internal timing. When MCLKRis connected continuously
high, the deviceis powered down.
MCLKX I 11 Transmit Master Clock. Mustbe 1.536MHz, 1.544MHzor 2.048MHz. May asynchronous with MCLKR.
BCLKX I 12 Thebit clock which shifts outthe PCM dataon DX. May vary from 64KHz 2.048MHz, but mustbe synchronous with MCLKX. O 13 The TRI-STATEPCM data output whichis enabledby FSX.
FSX I 14 Transmit frame sync pulse input which enables BCLKXto shift outthe
PCM dataon DX.FSXisan 8KHz pulse train. See figures1 and2for
timing details.
TSX O 15 Open drain output which pulses low during the encoder time slot. Mustto groundedif not used.
ANLB I 16 Analog Loopback Control Input. Mustbesetto logic’0’for normal
operation. When pulledto logic’1’,the transmit filter inputis disconnected
from the outputof the transmit preamplifier and connectedtothe VPO+
outputof the receive power amplifier.
GSX O 17 Analog outputof the transmit input amplifier. Usedtoset gain externally.
VFXI- I 18 Inverting inputof the transmit input amplifier.
VFXI+ I 19 Non-inverting inputof the transmit input amplifier.
VBB S 20 Negative Power Supply Pin. VBB= -5V ±5%
(*)I: Input,O: Output,S: Power Supply.
TRI-STATEisa trademarkof National Semiconductor Corp.
ETC5064- ETC5064-X- ETC5067- ETC5067-X
FUNCTIONAL DESCRIPTIONPOWER-UP
When poweris first applied, power-on reset circuitry
initializes the device and placesit into the power-
down mode. All non-essential circuits are deacti-
vated and theDX and VFRO outputsare putin high
impedancestates.To power-upthe device,a logical
low level or clock must be applied to the
MCLKR/PDN pin and FSX and/or FSR pulses must present. Thus2 power-down control modes are
available. The firstisto pull the MCLKR/PDN pin
high; the alternativeisto hold both FSX and FSRin-
puts continuouslylow. The device will power-down
approximately2 ms after the last FSX pulse. The
TRI-STATE PCM data output, DX, will remain inthe
high impedance state until the second FSX pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock
andbit clock shouldbe usedfor both the transmit
and receive directions.Inthismode,a clockmustbe
appliedto MCLKX and the MCLKR/PDN pin canbe
used asa power-down control.A low level on
MCLKR/PDN powersup the device anda high level
powersdown thedevice.Ineither case,MCLKX will
beselectedas themasterclockfor boththe transmit
and receive circuits.Abit clockmustalsobe applied BCLKX and theBCLR/CLKSELcanbe usedto se-
lect the properinternal dividerfora master clockof
1.536 MHz, 1.544 MHzor 2.048 MHz. For 1.544
MHz operation, the device automatically compen-
satesfor the 193rd clock pulse each frame.
Witha fixed level onthe BCLKR/CKSEL pin, BCLKX
willbe selectedas thebit clockfor both the transmit
and receive directions. Table1 indicates the fre-
quenciesof operation which can be selected, de-
pendingon thestateofBCLKR/CLKSEL.In this syn-
chronousmode, thebit clock, BCLKX, maybe from kHzto2.048 MHz,but mustbe synchronouswith
MCLKX.
Each FSX pulse begins the encoding cycle and the
PCM data from the previousencodecycleis shift out the enabled DX outputon the positive edgeof
BCLKX. After8bit clock periods, the TRISTATEDX
outputis returnedtoa highimpedancestate.Withan
FSR pulse, PCM datais latched via the DR inputon
thenegativeedgeofBCLKX(or onBCKLR ifrunning).
FSX andFSR mustbe synchronouswith MCLKX/R.
ASYNCHRONOUS OPERATION
For asynchronousoperation, separate transmit and
receive clocks maybe applied. MCLKX and MCLKR
mustbe 2.048MHz forthe ETC5067or 1.536MHz,
1.544MHz for the ETC5064, and need notbe syn-
chronous.For best transmissionperformance,how-
ever,MCLKR shouldbe synchronouswith MCLKX,
which iseasilyachievedby applyingonly staticlogic
levelsto theMCLKR/PDN pin.Thiswill automatically
connectMCLKX toallinternalMCLKR functions(see
pin description). For 1.544 MHz operation, the de-
vice automaticallycompensatesfor the 193rd clock
pulse each frame. FSX starts each encoding cycle
and mustbe synchronouswith MCLKX and BCLKX.
FSR starts each decoding cycle and mustbe syn-
chronous with BCLKR.BCLKR mustbea clock, the
logic levels shownin Table1 are not validin asyn-
chronous mode. BCLKX and BCLKR may operate
from 64kHzto 2.048 MHz.
SHORT FRAME SYNC OPERATION
The device can utilize eithera short frame sync
pulse ora long frame syncpulse.Upon powerinitiali-
zation, the device assumesa short frame mode.In
this mode, both frame sync pulses. FSX and FSR,
mustbe onebit clock period long, with timing rela-
tionships specifiedin figure2. With FSX high during falling edgeof BCLKR, the next rising edgeof
BCLKX enables the DX TRI-STATE output buffer,
which willoutputthesignbit.The followingsevenris-
ing edges clock out the remaining seven bits, and
the next falling edge disables the DX output. With
FSR high duringa falling edgeof BCLKR (BCLKXin
synchronousmode), thenext falling edgeof BCLKR
latchesin the sign bit. The following seven falling
edges latchin the seven remaining bits. Both de-
vices may utilize the short frame sync pulsein syn-
chronousor asynchronousoperatingmode.
LONG FRAME SYNC OPERATION use the long frame mode, both the frame sync
pulses,FSX andFSR, must bethreeormorebit clock
periods long, with timing relationships specifiedin
Table1: Selectionof Master Clock Frequencies.
BCLKR/CLKSEL
Master Clock
Frequency Selected
ETC5067
ETC5067-X
ETC5064
ETC5064-XClocked 2.048MHz 1.536MHzor
1.544MHz 1.536MHzor
1.544MHz
2.048MHz(or open circuit) 2.048MHz 1.536MHzor
ETC5064- ETC5064-X- ETC5067- ETC5067-X
pulses are being used. For64 kHz operation, the
frame sync pulses mustbe kept lowfora minimum 160ns (see Fig 1). The DX TRI-STATE output
bufferis enabledwith the rising edgeof FSXor the
rising edgeof BCLKX, whichever comes later, and
the firstbit clocked outis the sign bit. The following
seven BCLKX rising edges clock out the remaining
seven bits. The DX outputis disabledby the falling
BCLKX edge following the eighth rising edge,orby
FSX goinglow, whichevercomes later.Arising edge
onthereceiveframe syncpulse, FSR, willcause the
PCM dataat DRtobe latchedin on the next eight
falling edgesof BCLKR (BCLKxin synchronous
mode).Bothdevices may utilize the longframesync
pulsein synchronousor asynchronous mode.
TRANSMIT SECTION
Thetransmitsectioninputisan operationalamplifier
with provisionfor gain adjustmentusingtwo external
resistors,seefigure4. Thelow noiseandwideband-
width allow gainsin excessof 20 dB across the
audio passbandtobe realized. Theop amp drives unity gain filter consistingof RC active pre-filter,
followed by an eighth order switched-capacitor
bandpass filter directly drives the encodersample-
and-hold circuit. The A/Disof companding type ac-
cordingto A-law (ETC5067 and ETC5067-X)orμ-
law (ETC5064 and ETC5064-X) coding conven-
tions.A precision voltage referenceis trimmedin
manufacturingto providean input over load (tMAX) nominally 2.5V peak (see tableof Transmission
Characteristics). The FSX frame sync pulsecontrols
thesamplingof thefiler output,andthenthe succes-
sive-approximationencodingcyclebegins.The8-bit
codeis then loaded intoa buffer and shifted out
throughDXat thenext FSX pulse.the total encoding
delaywillbe approximately165μs (dueto the trans-
mit filter) plus 125μs (dueto encodingdelay), which
totals 290μs. Any offset voltagedueto the filtersor
comparatoris cancelledby signbit integration.
RECEIVE SECTION
The receive section consistofan expanding DAC
which drivesa fifth order switched-capacitor low
passfilter clockedat 256kHz. The decoderis A-law
(ETC5067 and ETC5067-X)or μ–law (ETC5064
and ETC5064-X) and the5th orderlow pass filter
correctsfor the sin x/x attenuation dueto the 8kHz
sample and hold. The filteris then followedbya2 order RC active post-filter and power amplifier
capableof drivinga 600Ω loadtoa levelof 7.2dBm.
The receive sectionis unity-gain. Upon the oc-
curenceof FSR, the dataat theDR inputis clocked on the falling edgeof the next eight BCLKR
(BCKLX) periods.Atthe endofthedecodertime slot,
the decoding cycle begins, and 10μs later the de-
coder DACoutputis updated.Thetotal decoder de-
layis about10μs (decoder up-date) plus 110μs (fil-
ter delay) plus 62.5μs (1/2 frame), which gives ap-
proximately 180μs.
RECEIVE POWER AMPLIFIERS
Two invertingmode power amplifiers are provided
for directly drivinga matched line interface trans-
former. The gainof the first power amplifier canbe
adjustedto boostthe± 2.5Vpeakoutputsignalfrom
the receive filter up± 3.3V peak intoan unbalanced
300Ω load, or±4.0Vintoan unbalanced15kΩ load.
The second power amplifieris internally connected unity-gain inverting modeto give 6dBof signal
gainfor balancedloads. Maximumpower transferto 600Ω subscriber line terminationis obtainedby
differientially drivinga balanced transformer witha2 :1 turns ratio,as shownin figure4.A total peak
powerof 15.6dBmcanbe deliveredto the load plus
termination. Both power amplifier canbe powered
down independentlyfromthe PDN input byconnect-
ing the VPI inputto VBB saving approximately12of power.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value UnitVCC VCCto GNDA 7 V
VBB VBBto GNDA -7 V
VIN,VOUT Voltageat any Analog Inputor Output VCC +0.3to VBB -0.3 V
Voltageat any Digital Inputor Output VCC +0.3to GNDA -0.3 V
Toper Operating Temperature Range:
ETC5064/67
ETC5064-X/67-X-25to +125
-40to +125
Tstg Storage Temperature Range -65to +150 °C
Lead Temperature (soldering,10 seconds) 300 °C
ETC5064- ETC5064-X- ETC5067- ETC5067-X
ELECTRICAL OPERATING CHARACTERISTICSVCC =5.0V±5%, VBB =-5V±5%, GNDA =0V,TA =0°Cto70°C (ETC5064-X/67-X:TA =–40°Cto 85°),unless
otherwisenoted; typical characteristicsspecifiedat VCC= 5.0V, VBB =-5.0V,TA =25°C;all signals are refer-
encedto GNDA.
DIGITAL INTERFACE (All devices)
Symbol Parameter Min. Typ. Max. UnitVIL Input Low Voltage 0.6 V
VIH Input High Voltage 2.2 V
VOL Output Low Voltage= 3.2 mA DX= 3.2 mA, Open Drain TSX
VOH Output High Voltage= 3.2 mA DX 2.4 V
IIL Input Low Current (GNDA≤ VIN≤VIL )all digital inputs
Except BCLKR
–10 10 μA
IIH Input High Current (VIH≤ VIN≤ VCC) Except ANLB –10 10 μA
IOZ Output Currentin High Impedance State (TRI-STATE)
(GNDA≤VO≤ VCC)DX –10 10 μA
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices)
Symbol Parameter Min. Typ. Max. UnitIIXA Input Leakage Current VFxI+or VFxI– 2.5V≤V≤+ 2.5V) 200 200 nA
RIXA Input Resistance VFXI+or VFXI– 2.5V≤V≤+ 2.5V) MΩ
ROXA Output Resistance (closed loop, unity gain) 1 3 Ω
RLXA Load Resistance GSX 10 kΩ
CLXA Load Capacitance GSX 50 pF
VOXA Output Dynamic Range (RL≥10 kΩ)GSX –2.8 +2.8 V
AVXA Voltage Gain (VFXI+to GSX) 5000 V/V
FUXA Unity Gain Bandwidth 1 2 MHz
VOSXA Offset Voltage –20 20 mV
VCMXA Common-mode Voltage –2.5 2.5 V
CMRRXA Common-mode Rejection Ratio 60 dB
PSRRXA Power Supply Rejection Ratio 60 dB
ANALOG INTERFACE WITH RECEIVE FILTER (all devices)
Symbol Parameter Min. Typ. Max. UnitRORF Output Resistance VFRO1 3 Ω
RLRF Load Resistance (VFRO=± 2.5V) 10 kΩ
CLRF Load Capacitance 25 pF
VOSRO Output DC Offset Voltage – 200 200 mV
ETC5064- ETC5064-X- ETC5067- ETC5067-X
ANALOG INTERFACE WITH POWER AMPLIFIERS (all devices)
Symbol Parameter Min. Typ. Max. UnitIPI Input Leakage Current(– 1.0V≤ VPI≤ 1.0V) – 100 100 nA
RIPI Input Resistance(– 1.0≤ VPI≤ 1.0V) 10 MΩ
VIOS Input Offset Voltage –25 25 mV
ROP Output Resistance (inverting unity–gainat VPO+or VPO– )1 Ω Unity–gain Bandwidth, Open Loop (VPO–) 400 kHz
CLP Load Capacitance (VPO+or VPO–to GNDA)≥ 1500Ω= 600Ω= 300Ω
GAp+ Gain VPO–to VPO+to GNDA, Levelat VPO–=1.77 Vrms3 dBmO)1 V/V
PSRRp Power Supply Rejectionof VCCor VBB
(VPO– connectedto VPI) kHz–4 kHz kHz–50 kHz
POWER DISSIPATION (all devices)
Symbol Parameter Min. Typ. Max. UnitICC0 Power-down Currentat
ETC6064/67
ETC5064-X/67-X1.5 mA
IBB0 Power-down Currentat
ETC6064/67
ETC5064-X/67-XICC1 Active Currentat
ETC6064/67
ETC5064-X/67-XIBB1 Active Currentat
ETC6064/67
ETC5064-X/67-XELECTRICAL OPERATING CHARACTERISTICS (Continued)
ETC5064- ETC5064-X- ETC5067- ETC5067-X
All TIMING SPECIFICATIONS
Symbol Parameter Min. Typ. Max. Unit1/tPM Frequencyof master clocks
MCLKX and MCLKR
Dependson the device used and the
BCLKR/CLKSEL Pin
MHz
tWMH Widthof Master Clock High MCLKX and MCLKR 160 ns
tWML Widthof Master Clock Low MCLKX and MCLKR 160 ns
tRM Rise Timeof Master Clock MCLKX and MCLKR 50 ns
tFM Fall Timeof Master Clock MCLKX and MCLKR 50 ns
tPB PeriodofBit Clock 485 488 15.725 ns
tWBH WidthofBit Clock High (VIH= 2.2V) 160 ns
tWBL WidthofBit Clock Low (VIL= 0.6V) 160 ns
tRB Rise TimeofBit Clock (tPB= 488ns) 50 ns
tFB Fall TimeofBit Clock (tPB= 488 ns) 50 ns
tSBFM Set-up time from BCLKX highto MCLKX falling edge.
(firstbit clock afterthe leading edgeof FSX)
100 ns
tHBF Holding Time fromBit ClockLowto the Frame Sync
(long frame only)
0ns
tSFB Set-up Time from Frame SynctoBit Clock (long frame only) 80 ns
tHBFI Hold Time from 3rd PeriodofBit Clock FSXor FSR
Lowto Frame Sync (long frame only)
100 ns
tDZF Delay Timeto valid data from FSXor BCLKX, whichever
comes later and delay time from FSXto data output disabled
(CL=0pFto 150 pF) 165 ns
tDBD Delay Time from BCLKX highto data valid
(load= 150pF plus2 LSTTL loads) 150 ns
tDZC Delay Time from BCLKX lowto data output disabled 50 165 ns
tSDB Set-up Time fromDR validto BCLKR/X low 50 ns
tHBD Hold Time from BCLKR/X lowtoDR invalid 50 ns
tHOLD Holding Time fromBit Clock Highto Frame Sync (short frame only) 0 ns
tSF Set-up Time from FSX/Rto BCLKX/R Low
(short frame sync pulse)- Note1 ns
tHF Hold Time from BCLKX/R Lowto FSX/R Low
(short frame sync pulse)- Note1
100 ns
tXDP Delay Timeto TSX low (load= 150pF plus2 LSTTI loads) 140 ns
tWFL Minimum Widthofthe Frame Sync Pulse (low level)
(64 bit/s operating mode)
160 ns
Note: 1.For short frame sync timing. FSX and FSR mustgo high while their respectivebit clocks are high.
Figure1:64k bits/s TIMING DIAGRAM. (see next page for complete timing)
ETC5064- ETC5064-X- ETC5067- ETC5067-X
Figure2: Short Frame Sync Timing.
ETC5064- ETC5064-X- ETC5067- ETC5067-X
