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ETC5054D-ETC5054FN-ETC5057D-ETC5057FN-ETC5057N
SERIAL INTERFACE CODEC/FILTER
ETC5054
ETC5057SERIAL INTERFACE CODEC/FILTER
COMPLETE CODEC AND FILTERING SYS-
TEM (DEVICE) INCLUDING:
– Transmit high-pass and low-pass filtering.
– Receive low-pass filter with sin x/x correction.
– Active RC noise filters
– μ-law or A-law compatible COder and DECoder.
– Internal precision voltage reference.
– Serial I/O interface.
– Internal auto-zero circuitry.
A-LAW 16 PINS (ETC5057FN, 20 PINS)
μ-LAW WITHOUT SIGNALING, 16 PINS
(ETC5054FN, 20 PINS)
MEETS OR EXCEEDS ALL D3/D4 AND
CCITT SPECIFICATIONS
±5V OPERATION
LOW OPERATING POWER - TYPICALLY 60
POWER-DOWN STANDBY MODE - TYPI-
CALLY 3 mW
AUTOMATIC POWER-DOWN
TTL OR CMOS COMPATIBLE DIGITAL IN-
TERFACES
MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY
0 to 70°C OPERATION
DESCRIPTIONThe ETC5057/ETC5054 family consists of A-law
and μ–law monolithic PCM CODEC/filters utilizing
the A/D and D/A conversion architecture shown in
the block diagram below, and a serial PCM inter-
face. The devices are fabricated using double-
poly CMOS process. The encode portion of each
device consists of an input gain adjust amplifier,
an active RC pre-filter which eliminates very high
frequency noise prior to entering a switched-ca-
pacitor band-pass filter that rejects signals below
200 Hz and above 3400 Hz. Also included are
auto-zero circuitry and a companding coder which
samples the filtered signal and encodes it in the
companded A-law or μ–law PCM format. The de-
code portion of each device consists of an ex-
panding decoder, which reconstructs the analog
signal from the companded A-law or μ–law code,
a low-pass filter which corrects for the sin x/x re-
sponse of the decoder output and rejects signals
above 3400 Hz and is followed by a single-ended
power amplifier capable of driving low impedance
loads. The devices require 1.536 MHz, 1.544
MHz, or 2.048 MHz transmit and receive master
clocks, which may be asynchronous, transmit and
receive bit clocks which may vary from 64 kHz to
2.048 MHz, and transmit and receive frame sync
pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry stand-
ard formats.
PIN CONNECTIONS (Top view)
BLOCK DIAGRAM
ETC5054 - ETC50572/18
PIN DESCRIPTION(*) I: Input, O: Output, S: Power Supply
(**) Pins 4,10,11 and 13 are not connected
TRI-STATE® is a trademark of National Semiconductor Corp.
ETC5054 - ETC50573/18
FUNCTIONAL DESCRIPTIONPOWER-UP
When power is first applied, power-on reset cir-
cuitry initializes the device and places it into
the power-down mode. All non-essential circuits
are deactivated and the DX and VFRO outputs are
put in high impedance states. To power-up the
device, a logical low level or clock must be ap-
plied to the MCLKR/PDN pin and FSX and/or FSR
pulses must be present. Thus, 2 power-down
control modes are available. The first is to pull the
MCLKR/PDN pin high ; the alternative is to hold
both FSX and FSR inputs continuously low. The
device will power-down approximately 2 ms after
the last FSX or FSR pulse. Power-up will occur on
the first FSX or FSR pulse. The TRI-STATE PCM
data output, DX, will remain in the high impedance
state until the second FSX pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master
clock and bit clock should be used for both the
transmit and receive directions. In this mode, a
clock must be applied to MCLKX and the
MCLKR/PDN pin can be used as a power-down
control. A low level on MCLKR/PDN powers up
the device and a high level powers down the de-
vice. In either case, MCLKX will be selected as
the master clock for both the transmit and receive
circuits. A bit clock must also be applied to BCLKX
and the BCLKR/CKSEL can be used to select the
proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz
operation, the device automatically compensates
for the 193rd clock pulse each frame. With a fixed
level on the BCLKR/CLKSEL pin, BCLKX will be
selected as the bit clock for both the transmit and
receive directions. Table 1 indicates the frequen-
cies of operation which can be selected, depend-
ing on the state of BCLKR/CLKSEL. In this syn-
chronous mode, the bit clock, BCLKX, may be
from 64 kHz to 2.048 MHz, but must be synchro-
nous with MCLKX.
Each FSX pulse begins the encoding cycle and
the PCM data from the previous encode cycle is
shifted out of the enabled DX output on the posi-
tive edge of BCLKX. After 8 bit clock periods, the
TRI-STATE DX output is returned to a high im-
pedance state. With and FSR pulse, PCM data is
latched via the DR input on the negative edge of
BCLKX (or BCLKR if running). FSX and FSR must
be synchronous with MCLKX/R.
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit
and receive clocks may be applied, MCLKX and
MCLKR must be 2.048 MHz for the ETC5057, or
1.536 MHz, 1.544 MHz for the ETC5054, and
need not be synchronous. For best transmission
performance, however, MCLKR should be syn-
chronous with MCLKX, which is easily achieved
by applying only static logic levels to the
MCLKR/PDN pin. This will automatically connect
MCLKX to all internal MCLKR functions (see pin
description). For 1.544 MHz operation, the device
automatically compensates for the 193rd clock
pulse each frame. FSX starts each encoding cycle
and must be synchronous with MCLKX and
BCLKX. FSR starts each decoding cycle and must
be synchronous with BCLKR. BCLKR must be a
clock, the logic levels shown in table 1 are not
valid in asynchronous mode. BCLKX and BCLKR
may operate from 64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The device can utilize either a short frame sync
pulse or a long frame sync pulse. Upon power in-
itialization, the device assumes a short frame
mode. In this mode, both frame sync pulses, FSX
and FSR, must be one bit clock period long, with
timing relationships specified in figure 2. With FSX
high during a falling edge of BCLKX the next ris-
ing edge of BCLKX enables the DX TRI-STATE
output buffer, which will output the sign bit. The
following seven rising edges clock out the remain-
ing seven bits, and the next falling edge disables
the DX output. With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the
next falling edge of BCLKR latches in the sign bit.
The following seven falling edges latch in the
seven remaining bits. Both devices may utilize the
short frame sync pulse in synchronous or asyn-
chronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync
pulses, FSX and FSR, must be three or more bit
clock periods long, with timing relationships speci-
fied in figure 3. Based on the transmit frame sync,
FSX, the device will sense whether short or long
frame sync pulses are being used. For 64 kHz op-
eration, the frame sync pulse must be kept low for
a minimum of 160 ns (see fig. 1). The DX TRI-
STATE output buffer is enabled with the rising
edge of FSX or the rising edge of BCLKX, which-
ever comes later, and the first bit clocked out is
the sign bit. The following seven BCLKX rising
Table 1: Selection of Master Clock Frequencies.
ETC5054 - ETC50574/18
edges clock out the remaining seven bits. The DX
output is disabled by the falling BCLKX edge fol-
lowing the eighth rising edge, or by FSX going
low, which-ever comes later. A rising edge on the
receive frame sync pulse, FSR, will cause the
PCM data at DR to be latched in on the next eight
falling edges of BCLKR (BCLKX in synchronous
mode). Both devices may utilize the long frame
sync pulse in synchronous or asynchronous
mode.
TRANSMIT SECTION
The transmit section input is an operational ampli-
fier with provision for gain adjustment using two
external resistors, see figure 6. The low noise and
wide bandwidth allow gains in excess of 20 dB
across the audio passband to be realized. The op
amp drives a unitygain filter consisting of RD ac-
tive pre-filter, followed by an eighth order
switched-capacitor bandpass filter clocked at 256
kHz. The output of this filter directly drives the en-
coder sample-and-hold circuit. The A/D is of com-
panding type according to A-law (ETC5057) or μ–
law (ETC5054) coding conventions. A precision
voltage reference is trimmed in manufacturing to
provide an input overload (tMAX) of nominally 2.5V
peak (see table of transmission characteristics).
The FSX frame sync pulse controls the sampling
of the filter output, and then the successive-ap-
proximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out
through DX at the next FSX pulse. The total en-
coding delay will be approximately 165 μs (due to
the transmit filter) plus 125μs (due to encoding
delay), which totals 290μs. Any offset vol-tage
due to the filters or comparator is cancelled by
sign bit integration.
RECEIVE SECTION
The receive section consists of an expanding
DAC which drives a fifth order switched-capacitor
low pass filter clocked at 256 kHz. The decoder is
A-law (ETC5057) or μ–law (ETC5054) and the
5th order low pass filter corrects for the sin x/x at-
tenuation due to the 8 kHz sample and hold.
The filter is then followed by a 2nd order RC ac-
tive post-filter and power amplifier capable of driv-
ing a 600Ω load to a level of 7.2 dBm. The re-
ceive section is unity-gain. Upon the occurence of
FSR, the data at the DR input is clocked in on the
falling edge of the next eight BCLKR (BCLKX) pe-
riods. At the end of the decoder time slot, the de-
coding cycle begins, and 10μs later the decoder
DAC output is updated. The total decoder delay
is ∼ 10μs (decoder update) plus 110μs (filter
delay) plus 62.5μs (1/2 frame), which gives ap-
proximately 180μs. A mute circuitry is a active
during 10ms when power up.
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL OPERATING CHARACTERISTICS VCC = 5.0 V ± 5 %, VBB = – 5.0 V ± 5%GNDA = 0 V,TA = 0 °C to 70 °C; Typical Characteristics Specified at VCC = 5.0 V, VBB = – 5.0 V, TA = 25 °C ; all signals
are referenced to GNDA.
ETC5054 - ETC50575/18
