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ESDALC6V1P6
QUAD LOW CAPACITANCE TRANSIL ARRAY FOR ESD PROTECTION
1/9
ESDALC6V1P6QUAD LOW CAPACITANCE TRANSIL™ ARRAY
FOR ESD PROTECTION
REV. 3
July 2004
MAIN APPLICATIONSWhere transient overvoltage protection in ESD
sensitive equipment is required, such as : Computers Printers Communication systems and cellular phones Video equipment
This device is particularly adapted to the
protection of symmetrical signals.
FEATURES 4 Unidirectional Transil™ functions Breakdown voltage VBR = 6.1 V min. Low diode capacitance (12pF @ 0V) Low leakage current < 500 nA Very small PCB area < 2.6 mm2
DESCRIPTIONThe ESDALC6V1P6 is a monolithic array
designed to protect up to 4 lines against ESD
transients.
The device is ideal for situations where board
space saving is required.
BENEFITS High ESD protection level High integration Suitable for high density boards
COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2 level 4:
15kV (air discharge)
8kV (contact discharge) MIL STD 883E-Method 3015-7: class3
25kV HBM (Human Body Model)
Order CodesASD™
FUNCTIONAL DIAGRAM
ESDALC6V1P6
ABSOLUTE RATING (Tamb = 25°C)
THERMAL RESISTANCES
ELECTRICAL CHARACTERISTICS (Tamb = 25°C)
Note 1: for a surge greater than the maximum values, the diode will fail in short-circuit.
ESDALC6V1P63/9
Fig. 1: Peak power dissipation versus initial
junction temperature.
Fig. 2: Peak pulse power versus exponential pulseduration (Tj initial = 25°C).
Fig. 3: Clamping voltage versus peak pulse
current (Tj initial = 25°C). Rectangular waveform
tp = 2.5µs.
Fig. 4: Peak forward voltage drop versus peak
forward current (typical values).
Fig. 5: Capacitance versus reverse applied
voltage (typical values).
Fig. 6: Relative variation of leakage current versusjunction temperature (typical values).
ESDALC6V1P6
TECHNICAL INFORMATION
1. ESD protection by ESDALC6V1P6With the focus of lowering the operation levels, the
problem of malfunction caused by the environment
is critical. Electrostatic discharge (ESD) is a major
cause of failure in electronic systems.
As a transient voltage suppressor, ESDALC6V1P6
is an ideal choice for ESD protection by
suppressing ESD events. It is capable of clamping
the incoming transient to a low enough level such
that any damage is prevented on the device
protected by ESDALC6V1P6.
ESDALC6V1P6 serves as a parallel protection
elements, connected between the signal line and
ground. As the transient rises above the operating
voltage of the device, the ESDALC6V1P6 becomes a low impedance path diverting the transient current
to ground.
The clamping voltage is given by the following formula:
VCL = VBR + Rd.IPP
As shown in figure A2, the ESD strikes are clamped by the transient voltage suppressor.
Fig. A2: ESD clamping behavior.To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical
dynamical resistance value Rd. By taking into account the following hypothesis:
we have:
The results of the calculation done VG = 8kV, RG = 330Ω (IEC61000-4-2 standard), VBR = 6.4V (typ.) and
Rd = 1.5Ω (typ.) give:
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be a few
tenths of volts during a few ns at the Vi/o side.G Rd ""and""R load Rd>>o⁄() VBR Rd+ VGG------×=o⁄() 42.8 Volts=
Fig. A: Application example.
ESDALC6V1P65/9
The measurements done here after show very clearly (figure A5) the high efficiency of the ESD protection:
the clamping voltage V(i/o) becomes very close to VBR (positive way, figure A5a) and -VF (negative way,
figure A5b).
One can note that the ESDALC6V1P6 is not only acting for positive ESD surges but, also, for negative
ones. For this kind of disturbances, it clamps close to ground voltage as shown in figure A5b.
Fig. A3: ESD test board. Fig. A4: ESD test condition.
Fig. A5: Remaining voltage during ESD surge.
ESDALC6V1P6
2. Crosstalk behaviorThe crosstalk phenomena are due to the coupling between 2 lines. Coupling factors ( β12 or β21 ) increase
when the gap across lines decreases, particularly in silicon dice. In the example above, the expected
signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG2. This part
of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This
phenomenon has to be taken into account when the drivers impose fast digital data or high frequency
analog signals. The perturbed line will be more affected if it works with low voltage signal or high load
impedance (few kΩ).
Figure A7 gives the measurement circuit for the analog crosstalk application. In figure 8, the curve shows
the effect of the cell I/O1 on the cell I/O4. In usual frequency range of analog signals (up to 100 MHz) the
effect on disturbed line is less than -55dB.
Fig. A6: Crosstalk phenomenon.
Fig. A7: Analog crosstalk test configuration. Fig. A8: Typical analog crosstalk response.
