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ESDA14V2SC5-ESDA14V2SC6-ESDA17SC6-ESDA19SC6-ESDA25SC6-ESDA5V3SC5-ESDA5V3SC6-ESDA6V1SC5-ESDA6V1SC6
QUAD TRANSIL ARRAY FOR ESD PROTECTION
ESDAxxSC5ESDAxxSC6QUAD TRANSIL ARRAY
FOR ESD PROTECTION
The ESDAxxSC5 and ESDAxxSC6 are monolithic
voltage suppressors designed to protect
components which are connectedto data and
transmission lines against ESD.
They clamp the voltage just above the logic level
supplyfor positive transients, andtoa diode drop
below ground for negative transient.
DESCRIPTIONWhere transient overvoltage protectionin ESD
sensitive equipmentis required, suchas: Computers Printers Communication systems Cellular phone handsets and accessories Other telephone set Set top boxes
APPLICATIONS
FUNCTIONAL DIAGRAMSOT23-5L
SOT23-6L
Application Specific Discretes
A.S.D.™
High ESD protection level:upto25kV
High integration
Suitablefor high density boards
BENEFITSIEC61000-4-2: level4
15kV (air discharge)
8kV (contact discharge)
MIL STD 883E-Method 3015-7: class3B
(human body model)
COMPLIES WITH THE FOLLOWING STAN-
DARDS:4 Unidirectional Transil™ Functions Low leakage current:IR max.<20 μAatVBR 500W Peak pulse power (8/20 μs)
FEATURES
ESDAxxSC5 / ESDAxxSC6
ABSOLUTE MAXIMUM RATINGS (Tamb= 25°C)
ELECTRICAL CHARACTERISTICS (Tamb= 25°C)
ESDAxxSC5 / ESDAxxSC6The ESDA family has been designedto clamp fast
spikes like ESD. Generally the PCB designers
needto calculate easily the clamping voltage VCL.
Thisis why we give the dynamic resistancein
additionto the classical parameters. The voltage
across the protection cell can be calculated with
the following formula:
VCL =VBR +RdIPP
Where Ippis thepeak current throughthe ESDA cell.
DYNAMIC RESISTANCE MEASUREMENTThe short durationof the ESD has ledusto prefer more adapted test wave,as below defined,to the
classical 8/20μs and 10/1000μs surges.
2.5s duration measurement wave. the valueof the dynamic resistance remains
stable fora surge duration lower than 20μs, the
2.5μs rectangular surge is well adapted. In
addition both rise and fall times are optimizedto
avoid any parasitic phenomenon during the
measurementof Rd.
CALCULATION OF THE CLAMPING VOLTAGE
USE OF THE DYNAMIC RESISTANCE
note1:Squarepulse,Ipp= 15A, tp=2.5μs.
note2:Δ VBR= αT*(Tamb -25°C) *VBR (25°C)
ESDAxxSC5 / ESDAxxSC6 25 50 75 100 125 1500.0
Ppp [Tj initial] / Ppp [Tj initial=25°C]
Fig. 1: Peak power dissipation versus initial
junction temperature. 10 100100
Ppp(W)
Fig.2: Peak pulse power versus exponential pulse
duration(Tj initial=25 °C).5 1015202530354045505560657075800.1
Ipp(A)
Fig. 3: Clamping voltage versus peak pulse
current(Tj initial=25 °C).
Rectangular waveform (tp= 2.5 μs). 5 10 20 5010
C(pF)
Fig. 4: Capacitance versus reverse applied
voltage (typical values). 50 75 100 1251
IR[Tj] / IR[Tj=25°C]
Fig.5: Relative variationof leakage current versus
junction temperature (typical values).
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.00.01
IFM(A)
Fig.6: Peak forward voltage drop versus peak
forward current (typical values).
ESDAxxSC5 / ESDAxxSC6Electrostatic discharge (ESD)isa major causeof
failurein electronic systems.
Transient Voltage Suppressors (TVS) arean ideal
choice for ESD protection. They are capableof
clamping the incoming transient overvoltagetoa
low enough level such that damage to the
protected semiconductoris prevented.
Surface mount TVS arrays offer the best choicefor
minimal lead inductance.
They serve as parallel protection elements,
connected between the signal line and ground.As
the transient rises above the operating voltageof
the device, the TVS array becomesa low
impedance path diverting the transient currentto
ground.
ESD protectionby ESDAXXXSCXThe ESDAxxSCx arrayis the ideal board level
protection of ESD sensitive semiconductor
components.
The tiny SOT23-5L and SOT23-6L packages allow
design flexibilityin the high density boards where
the space savingisata premium. This enablesto
shorten the routing and contributesto hardening
against ESD.
ADVICE FOR OPTIMIZING CIRCUIT BOARD
LAYOUTCircuit board layoutisa critical design stepin the
suppression of ESD induced transients. The
following guidelines are recommended: The ESDAxxSC5/6 shouldbe placedas closeas
possibleto the input terminalsor connectors. The path length between the ESD suppressor
and the protected line shouldbe minimized All conductive loops, including power and
ground loops shouldbe minimized The ESD transient return pathto ground should keptas shortas possible. Ground planes shouldbe used whenever possi-
ble.
ESDAxxSC5 / ESDAxxSC6
TECHNICAL INFORMATIONThe
ESDA19SC6is particularly optimizedto perform ESD protection. ESD protectionis achieved by
clamping the unwanted overvoltage. The clamping voltageis givenby the following formula: RICL BR dpp=+ ⋅ shownin figure A1, the ESD strikes are clampedby the transient voltage suppressor.
ESD PROTECTIONCircuit board layoutisa critical design stepin the suppressionof ESD induced transients. The following
guidelines are recommended: The ESDA19SC6 shouldbe placedas closeas possibleto the input terminalsor connectors. The path length between the ESD suppressor and the protected line shouldbe minimized. All conductive loops, including power and ground loops shouldbe minimized. The ESD transient return pathto ground shouldbe keptas shortas possible. Ground planes shouldbe used whenever possible.
ADVICE FOR OPTIMIZING CIRCUIT BOARD LAYOUT havea good approximationof the remaining voltagesat both VI/O side, we provide the typical
dynamical resistance value Rd.By taking into account the following hypothesis:> Rd and Rload> Rd have:
VOutput V R V d=+ ×
The resultsof the calculation donefor Vg=8 kV, Rg= 330Ω (IEC61000-4-2 standard), Vbr=19V (typ.)
and Rd= 0.80Ω (typ.) give:
VOuput= 38.4V
This confirms the very low remaining voltage across the devicetobe protected.Itis also importantto note
thatin this approximation the parasitic inductance effect was not taken into account. This couldbea few
tenthsof volts duringa few nanosecondsat the output side.
Fig. A1: ESD clamping behavior (example)
