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EMIF06-VID01F2
6-line EMI filter and ESD protection for display interfaces
April 2008 Rev 2 1/7
EMIF06-VID01F26-line IP AD™, low capacitance EMI filter and ESD protection
Features High efficiency EMI filtering
(-40 dB @ 900 MHz) Low line capacitance suitable for high speed
data bus Low serial resistance for camera impedance
adaptation Lead-free package Optimized PCB space occupation:
2.92 mm x 1.29 mm Very thin package: 0.65 mm High efficiency in ESD suppression on inputs
pins (IEC 61000-4-2 level 4) High reliability offered by monolithic integration High reduction of parasitic elements through
integration and wafer level packaging
Complies with the following standards: IEC 61000-4-2 Level 4 on input pins 15 kV (air discharge) 8 kV (contact discharge) MIL STD 883E - Method 3015-6 Class 3
ApplicationWhere EMI filtering in ESD sensitive equipment is
required: LCD and camera for mobile phones Computers and printers Communication systems MCU board
Figure 1. Pin layout (bump side)
Figure 2. Device configuration
DescriptionThe EMIF06-VID01F2 is a 6-line highly integrated
array designed to suppress EMI / RFI noise in all
systems subjected to electromagnetic
interference.
The EMIF06-VID01F2 Flip Chip packaging means
the package size is equal to the die size.
Additionally, this filter includes ESD protection
circuitry which prevents damage to the protected
device when subjected to ESD surges up to kV.
Characteristics EMIF06-VID01F22/7
1 Characteristics
Table 1. Absolute ratings (limiting values)
Table 2. Electrical characteristics (Tamb = 25 °C)
EMIF06-VID01F2 Characteristics 3/7
Figure 7. Junction capacitance versus reverse voltage applied (typical values)
Figure 3. S21 (dB) attenuation measurement Figure 4. Analog crosstalk measurement
Figure 5. ESD response to IEC 61000-4-2
(+15 kV air discharge) on one input in ) and on one output (Vout)
Figure 6. ESD response to IEC 61000-4-2
(-15 kV air discharge) on one input in ) and on one output (Vout)
Ordering information scheme EMIF06-VID01F24/7
Ordering information scheme
Figure 8. Ordering information scheme
3 Package informationIn order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
.
Figure 9. Flip Chip package dimensions
EMIF06-VID01F2 Package information 5/7
Figure 12. Flip Chip tape and reel specificationNote: More packing information is available in the application note
AN1235: “Flip Chip: Package description and recommendations for use”
AN1751: “EMI Filters: Recommendations and measurements”
Figure 10. Footprint recommendations Figure 11. Marking
Ordering information EMIF06-VID01F26/7
4 Ordering information
5 Revision history
Table 3. Ordering information
Table 4. Document revision history
