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EMIF06-1502M12
6-line low capacitance EMI filter and ESD protection
February 2008 Rev 4 1/10
EMIF06-1502M126-line IP AD™
low capacitance EMI filter and ESD protection in micro QFN package
Features EMI asymmetrical (I/O) low-pass filter High efficiency in EMI filtering Very low PCB space consuming:
2.5 mm x 1.5 mm Very thin package: 0.6 mm max High efficiency in ESD suppression on inputs
pins (IEC 61000-4-2 level 4) High reliability offered by monolithic integration High reducing of parasitic elements through
integration and wafer level packaging Lead-free package
Complies with following standards: IEC 61000-4-2 level 4 input pins 15 kV (air discharge) 8 kV (contact discharge) MIL STD 883G - Method 3015-7 Class 3A
(all pins)
ApplicationsWhere EMI filtering in ESD sensitive equipment is
required: LCD and camera for mobile phones Computers and printers Communication systems MCU boards
DescriptionEMIF06-1502M12 is a 6-line, highly integrated
device designed to suppress EMI/RFI noise in all
systems exposed to electromagnetic interference.
This filter includes ESD protection circuitry, which
prevents damage to the application when
subjected to ESD surges up to 15 kV on the input
pins.
Figure 2. Basic cell configurationTM: IPAD is a trademark of STMicroelectronics
Characteristics EMIF06-1502M122/10
1 Characteristics
Table 1. Absolute ratings (limiting values at Tamb = 25 °C unless otherwise specified)
Table 2. Electrical characteristics (Tamb = 25 °C)
Figure 3. S21 attenuation measurement Figure 4. Analog cross talk measurements
EMIF06-1502M12 Ordering information scheme 3/10
Figure 7. Line capacitance versus reverse voltage applied (typical value) Ordering information scheme
Figure 8. Ordering information scheme
Figure 5. ESD response to IEC 61000-4-2
(+15 kV air discharge) on one input
(Vin) and on one output (Vout)
Figure 6. ESD response to IEC 61000-4-2 15 kV air discharge) on one input
(Vin) and on one output (Vout)
Package information EMIF06-1502M124/10
3 Package information Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
.
Table 3. QFN 2.5 x 1.5 package dimensions
EMIF06-1502M12 Package information 5/10
Figure 11. Tape and reel specificationNote: Product marking may be rotated by 90° for assembly plant differentiation. In no case should
this product marking be used to orient the component for its placement on a PCB. Only pin1
mark is to be used for this purpose.
Recommendation on PCB assembly EMIF06-1502M126/10
Recommendation on PCB assembly
4.1 Stencil opening design General recommendation on stencil opening design
a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 12. Stencil opening dimensionsb) General design rule
Stencil thickness (T) = 75 ~ 125 µm
2. Reference design
a) Stencil opening thickness: 100 µm
b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%.
c) Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 13. Recommended stencil window positionAspect Ratio W----- 1.5≥=
Aspect Area LW×L W+ ()---------------------------- 0.66≥=
