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EMIF03-SIM01
3 LINES EMI FILTER INCLUDING ESD PROTECTION
EMIF03-SIM01July 2002 - Ed: 6A
IEC61000-4-2 15kV (air discharge)kV (contact discharge) input& output pins.
COMPLIESWITH THEFOLLOWING STANDARDS:
PIN CONFIGURATION (Ball side) 3 lines symetrical (I/O) low-pass-filter High efficiencyin EMI filtering Very low PCB space consuming: 1.6x 1.6 mm Very thin package: 0.65 mm High efficiencyin ESD suppressionon both input output PINS (IEC61000-4-2 level4) High reliability offeredby monolithic integration High reducingof parasitic elements through inte-
gration& wafer level packaging.
BENEFITS3 LINES EMI FILTER
INCLUDING ESD PROTECTIONA.S.D.TM
EMI filtering protection and ESDfor: SIM Interface (Subscriber identify Module)
MAIN APPLICATIONSThe EMIF03-SIM01isa highly integrated array
designed to suppress EMI/ RFI noisein all
systems subjected to electromagnetic
interferences.
The EMIF03-SIM01 flip-chip packaging means the
package sizeis equalto the die size. That's why
EMIF03-SIM01isa very small device.
Additionally, this filter includesan ESD protection
circuitry which prevents the protected device from
destruction when subjectedto ESD surges upto kV.
DESCRIPTION: ASDisa trademarkof STMicroelectronics.
EMIF03-SIM01
Schematic
Aplac model
Filtering behavior
EMIF03-SIM01
ESD responseto IEC61000-4-2 (15kV air discharge)
Capacitance versus reverse applied voltage.
ABSOLUTE MAXIMUM RATINGS (Tamb =25°C)
EMIF03-SIM01
ELECTRICALCHARACTERISTICS (Tamb=25°C)
TECHNICAL INFORMATIONThe EMIF03-SIM01is firstly designedasan EMI RFI filter. This low-pass filteris characterized the following parameters: Cut-off frequency Insertion loss High frequency rejection
Figure A1shows that attenuationis better than
-20dBat mobile phone frequencies (800MHzto
2.5GHz).
FREQUENCY BEHAVIOR
Fig. A1: Frequency response curve
EMIF03-SIM01
Fig. A2: Measurements conditions addition with the filtering the EMIF03-SIM01is particularly optimizedto perform ESD protection.
ESD protectionis basedon the useof device which clampsat: RIcl br d pp=+ ⋅
This protection functionis splittedin2 stages.As shownin Figure A3, the ESD strikes are clampedby the
first stage S1 and thenits remaining overvoltageis appliedto the second stage through the resistorR.
Sucha configuration makes the output voltage very lowat the Vout level.
ESD PROTECTION
Fig. A3: ESD clamping behavior
EMIF03-SIM01 havea good approximationof the remaining voltagesat both Vin and Vout stages, we give the typical
dynamic resistance value Rd. By taking into account these following hypothesis: R>>Rd, Rg>>Rd and
Rload>>Rd,it gives these formulas:
Vinput RV RV
gbr d g= ⋅+⋅
Voutput RV R V d in= ⋅+⋅
The resultsof the calculation done for an IEC 1000-4-2 Level4 Contact Discharge surge (Vg=8kV,
Rg=330Ω) and Vbr=7V (typ.) give:
Vinput= 43.36V
Voutput= 7.65V(R= 100Ω)
8.38V(R= 47Ω)
This confirms the very low remaining voltage across the devicetobe protected.Itis also importantto note
thatin this approximation the parasitic inductance effect was not taken into account. This couldbe few
tenthsof volts during fewnsat the Vin side. This parasitic effectis not presentat the Vout side due the low
current involved after the series resistanceR.
The early ageing and destructionof IC’sis often dueto latch-up phenomena which mainly inducedby
dV/dt. Thankstoits RC structure, the EMIF03-SIM01 providesa high immunityto latch-upby integrationof
fast edges. (Please referto the responseof the EMIF03-SIM01toa30ns edgeon Fig. A9)
The measurements done here after show very clearly (Fig. A5a& A5b) the high efficiencyof the ESD
protection: almostno influenceof the parasitic inductanceson Vout stage Vout clamping voltage very closeto Vbrfor positive surge and closeto groundfor negative one
LATCH-UP PHENOMENA
Fig. A4: Measurements conditions
