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EMIF01-10018W5
EMI FILTER INCLUDING ESD PROTECTION
EMIF01-10018W5September 1999 - Ed: 1
IEC 1000-4-2 15kV (air discharge)
level 4 8 kV (contact discharge)
MIL STD 883C - Methode 3015-6 Class 3
COMPLIES WITH THE FOLLOWING STANDARD:
FUNCTIONAL DIAGRAMCost-effectiveness compared to discrete solution
EMI bi-directional low-pass filter
High efficiency in ESD suppression.
High flexibility in the design of high density boards
Very low PCB space consuming : 4.2 mm2 typically
High reliability offered by monolithic integration
BENEFITSEMI FILTER
INCLUDING ESD PROTECTION
Application Specific Discretes
A.S.D.TM
Where EMI filtering in ESD sensitive equipment is required :
Computers and printers
Communication systems
Mobile phones
MCU Boards
MAIN APPLICATIONSThe EMIF01-10018W5 is a highly integrated array
designed to suppress EMI / RFI noise in all systems
subjected to electromagnetic interferences.
Additionally, this filter includes an ESD protection circuitry
which prevents the protected device from destruction when
subjected to ESD surges up to 15 kV.
DESCRIPTION
TM : ASD is trademark of STMicroelectronics.
Filtering behavior ESD response to IEC1000-4-2 (16 kV air discharge)1/10
ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C)Note 1 : to calculate the ESD residual voltage, please refer to the paragraph "ESD PROTECTION" on pages 4 & 5
ELECTRICAL CHARACTERISTICS (Tamb = 25 °C)
EMIF01-10018W52/10
FREQUENCY BEHAVIORThe EMIF01-10018W5 is firstly designed as an EMI/RFI filter. This low-pass filter is characterized by the following
parameters:
- Cut-off frequency
- Insertion loss
- High frequency rejection
Fig A1: EMIF01-10018W5 frequency response curve.
Fig. A2: Measurement conditions
TECHNICAL INFORMATIONFigure A1 gives these parameters, in particular the signal rejection at the GSM frequency is about
-24dB @ 900MHz
-20dB @ 1800MHz
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ESD PROTECTIONIn addition to its filtering function, the EMIF01-10018W5 is particularly optimized to perform ESD protection.
ESD protection is based on the use of device which clamps at :
VCL = VBR + Rd.IPP
This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the first stage S1 and
then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output
voltage very low at the Vout level.
Fig. A3: ESD clamping behavior.
Fig. A4: Measurement conditionsTo have a good approximation of the remaining voltages at both Vin and Vout stages, we provide the typical dynamical
resistance value Rd. By taking into account these following hypothesis : R>>Rd, RG>>Rd and Rload>>Rd, it gives these
formulas:
Vin = Rg.Vbr+Rd.Vg
Vout = R.Vbr+Rd.Vin
The results of the calculation done for an IEC 1000-4-2 Level 4 Contact Discharge surge (Vg=8kV, Rg=330Ω) and VBR=7V
(typ.) give:
Vin = 31.2 V
Vout = 7.3 VThis confirms the very low remaining voltage across the device to be protected. It is also important to note that in this
approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at
the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R.
LATCH-UP PHENOMENAThe early ageing and destruction of IC’s is often due to latch-up phenomena which mainly induced by dV/dt. Thanks to
its RC structure, the EMIF01-10018W5 provides a high immunity to latch-up by integration of fast edges. (Please see the
response of EMIF01-10018W5 to a 3 ns edge on Fig. A9)
The measurements done here after show very clearly (Fig. A5a & A5b) the high efficiency of the ESD protection : - almost no influence of the parasitic inductances on Vout stage
- Vout clamping voltage very close to Vbr
EMIF01-10018W54/10
Fig. A6: Rd measurement current wave
Fig. A5: Remaining voltage at both stages S1 (Vin) and S2 (Vout) during ESD surgePlease note that the EMIF01-10018W5 is not only acting for positive ESD surges but also for negative ones. For negatives
surges, it clamps close to ground voltage as shown in Fig. A5b.
NOTE: DYNAMIC RESISTANCE MEASUREMENTAs the value of the dynamic resistance remains stable for
a surge duration lower than 20μs, the 2.5μs rectangular
surge is well adapted. In addition both rise and fall times
are optimized to avoid any parasitic phenomenon during
the measurement of Rd.
EMIF01-10018W55/10
Fig. A7: Crosstalk phenomena
CROSSTALK BEHAVIOR
1- Crosstalk phenomena
2- Digital Crosstalk
Fig. A8: Digital crosstalk measurement
Fig. A9: Digital crosstalk resultsThe crosstalk phenomena are due to the coupling between 2 lines. The coupling factor ( β12 or β21 ) increases when the
gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is α2VG2, in
fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the
crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose
fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works
with low voltage signal or high load impedance (few kΩ). The following chapters give the value of both digital and analog
crosstalk.
Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application.
Figure A9 shows that in such a condition signal from 0 to 5V and rise time of few ns, the impact on the disturbed line is less
than 50mV peak to peak. No data disturbance was noted on the concerned line.The measurements performed with falling
edges gives an impact within the same range.
EMIF01-10018W56/10
