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EMIF01-10005W5
EMI FILTER, INCLUDING ESD PROTECTION
EMIF01-10005W5May 1999 - Ed: 1
IEC 1000-4-2 15kV (air discharge)
8 kV (contact discharge)
COMPLIES WITH THE FOLLOWING STANDARD:
FUNCTIONAL DIAGRAMCost-effectiveness compared to discrete solution
EMI bi-directional low-pass filter
High efficiency in ESD suppression.
High flexibility in the design of high density boards
Very low PCB space consuming : 4.2 mm2 typically
High reliability offered by monolithic integration
BENEFITSEMI FILTER
INCLUDING ESD PROTECTION
Application Specific Discretes
A.S.D.TM
Where EMI filtering in ESD sensitive equipment is required :
Computers and printers
Communication systems
Mobile phones
MCU Boards
MAIN APPLICATIONSThe EMIF01-10005W5 is a highly integrated array
designed to suppress EMI / RFI noise in all systems
subjected to electromagnetic interferences.
Additionally, this filter includes an ESD protection circuitry
which prevents the protected device from destruction when
subjected to ESD surges up to 15 kV.
DESCRIPTION
TM : ASD is trademark of STMicroelectronics.
ESD response to IEC1000-4-2 (16 kV air discharge) Filtering response1/10
ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C)Note 1 : to calculate the ESD residual voltage, please refer to the paragraph "ESD PROTECTION" on pages 4 & 5
ELECTRICAL CHARACTERISTICS (Tamb = 25 °C)
EMIF01-10005W52/10
TECHNICAL INFORMATION
FREQUENCY BEHAVIORThe EMIF01-10005W5 is firstly designed as an EMI/RFI filter. This low-pass filter is characterized by the following
parameters:
- Cut-off frequency
- Insertion loss
- High frequency rejection
Figure A1 gives these parameters, in particular the signal rejection at the GSM frequency is about -24dB at 900MHz,
Fig A1: EMIF01-10005W5 frequency response curve.
Fig A2: Measurement conditions
EMIF01-10005W53/10
ESD PROTECTIONIn addition to its filtering function, the EMIF01-10005W5 is particularly optimized to perform ESD protection.
ESD protection is based on the use of device which clamps at :
VCL = VBR + Rd.IPP
This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the first stage S1 and
then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output
voltage very low at the Vout level.
To have a good approximation of the remaining voltages at both Vin and Vout stages, we provide the typical dynamical
resistance value Rd. By taking into account these following hypothesis : R>>Rd, RG>>Rd and Rload>>Rd, it gives these
formulas:
Vin = Rg.Vbr+Rd.Vg
Vout = R.Vbr+Rd.Vin
The results of the calculation done for VG=8kV, RG=330Ω (IEC1000-4-2 standard) and VBR=7V (typ.) give:
Vin = 31.2 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this
approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at
the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R.
Fig A3 : ESD clamping behavior
Fig A4 : Measurement conditions
EMIF01-10005W54/10
Please note that the EMIF01-10005W5 is not only acting
for positive ESD surges but also for negative ones. For
these kind of disturbances it clamps close to ground
voltage as shown in Fig. A5b.
NOTE: DYNAMIC RESISTANCE MEASUREMENTAs the value of the dynamic resistance remains stable for
a surge duration lower than 20μs, the 2.5μs rectangular
surge is well adapted. In addition both rise and fall times
are optimized to avoid any parasitic phenomenon during
the measurement of Rd.
Fig A5 : Remaining voltage at both stages S1 (Vin) and S2 (Vout) during ESD surge
Fig A6 : Rd measurement current waveThe measurements shown here after illustrate very clearly (Fig. A5a) the high efficiency of the ESD protection :
- no influence of the parasitic inductances on Vout stage
- Vout clamping voltage very close to VBR
EMIF01-10005W55/10
Fig A7 : Crosstalk phenomena
CROSSTALK BEHAVIOR
1- Crosstalk phenomena
2- Digital CrosstalkFigure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application.
Figure A9 shows that in such a condition signal from 0 to 5V and rise time of 3 ns, the impact on the disturbed line is less
than 100mV peak to peak. No data disturbance was noted on the concerned line. The same results were obtained with
falling edges.
Fig A8 : Digital crosstalk measurement
Fig A9 : Digital crosstalk results
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